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Micro spiral inductor를 이용한 2.5Gb/s급 2:1 Multiplexer 설계
김선중,최정명,범진욱,Kim, Sun-Jung,Choi, Jung-Myung,Burm, Jin-Wook 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.8
A 2.5Gb/s 2:1 multiplexer(MUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. On-chip micro spiral inductor was designed to maximize the inductive peaking effect without increasing the chip area much. The designed 4.7 nH micro-spiral inductor was $20\times20{\mu}m2$ in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 23% and 3% respectively using the micro spiral inductors for 1.25Gb/s signal. For 2.5 Gb/s signal, fall and rise time was improved 5.3% and 3.5% respectively. It consumed 61mW and voltage output swing was 1$180mV_{p-p}$ at 2.5Gb/s. [ $0.18{\mu}m$ ] CMOS공정을 이용하여 supply voltage 1.8V에서 2.5Gb/s 이상의 데이터 처리속도를 가지는 2:1 Multiplexer(MUX) 설계를 하였다. High speed 동작을 위한 주파수의 한계를 극복하기 위해서 4.7 nH의 on-chip micro spiral micro inductor $(20\times20{\mu}m2)$가 설계 되었고, 10개 이상의 inductor를 사용하고도 칩 면적 증가가 거의 없으면서 inductive peaking 효과를 극대화할 수 있었다. 칩 측정은 on-wafer로 진행되었고, micro spiral inductor가 있는 2:1 MUX와 그것이 없는 2:1 MUX 각각 측정하여 그 결과를 비교하였다. 측정결과 micro spiral inductor를 가진 2:1MUX가 rise time과 fall time이 1.25Gb/s에서는 rise time이 23%, fall time은 3%의 peaking 개선 효과가 있는 것을 확인하였다. 2.5Gb/s에서는 fall time이 약 5.3%, rise time 3.5%의 개선 효과를 보았다. 전체 소비전력은 61.2mW, 2.5Gb/s에서 voltage output swing은 $180mV_{p-p}$로 측정되었다.
Current Mode Signaling 방법을 이용한 $0.18{\mu}m$ CMOS 3.2-Gb/s 4-PAM Serial Link Receiver
이정준,정지경,범진욱,정영한,Lee, Jeong-Jun,Jeong, Ji-Kyung,Burm, Jin-Wook,Jeong, Young-Han 대한전자공학회 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.10
본 논문은 $0.18{\mu}m$ CMOS 공정을 이용하여 3.2 Gb/s serial link receiver를 설계하였다. High-speed links의 performance를 제한하는 가장 큰 요소는 transmission channel bandwidth, timing uncertainty가 있다. 이러한 문제점을 해결하기 위한 방법으로 multi-level signaling(4-PAM)을 이용하였다. 추가적으로 전송속도를 높이고 BER를 낮추기 위한 방법으로 current-mode amplifier, CML sampling latch를 사용하였다. 4-PAM receiver의 최대 데이터 전송속도는 3.2 Gb/s이다. BER은 $1.0{\times}10^{-12}$ 이하이며 chip size는 $0.5\;{\times}\;0.6\;mm^2$이고 1.8 V supply voltage에서 49mA current를 소모한다. The design of a 3.2 Gb/s serial link receiver in $0.18{\mu}m$ CMOS process is presented. The major factors limiting the performance of high-speed links are transmission channel bandwidth, timing uncertainty. The design uses a multi-level signaling(4-PAM) to overcome these problems. Moreover, to increase data bit-rate and lower BER, we designed this circuit by using a current mode amplifier, Current-mode Logic(CML) sampling latches. The 4-PAM receiver achieves 3.2 Gb/s and BER is less than $1.0\;{\times}\;10^{-12}$. The $0.5\;{\times}\;0.6\;mm^2$ chip consumes 49 mA at 3.2 Gb/s from a 1.8-V supply.
의료 기기용 10bit, 100Ks/S Successive Approximation A/D Converter 설계
김재운(Jae-Woon Kim),범진욱(Jin-Wook Burm),임신일(Shin-Il Lim) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.10
This paper describes the design of a 10-bit 100 KSample/S CMOS AID Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional 10-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4㎽. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190㎼ at the supply voltage of 1.8V with the 0.18㎛ general CMOS technology.
Nested-chopping 기법을 이용한 Instrumentation Amplifier 설계
이준규(Jun-Gyu Lee),범진욱(Jin-Wook Burm),임신일(Shin-Il Lim) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.10
In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 ㎵. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 ㎽ at the supply voltage of 3.3V with the 0.35㎛ general CMOS technology. The die area of implemented chip was 530㎛ × 300㎛.
이준규(Jun-Gyu Lee),범진욱(Jin-Wook Burm),임신일(Shin-Il Lim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
In this paper, we describe a chip design technique for sphygmograph by using the same principles of pulse oximetry. TIA(Trans-Impedance Amplifier), notch filter, HPF and LPF were implemented with rail-to-rail folded cascode amplifier. The total power consumption of designed chip was 12.8㎽ at the supply voltage of 3.3V with the 0.35㎛ general CMOS technology. The die area of implemented chip was 3㎜×0.5㎜.
Spiral micro inductor를 사용한 20Gb/s급 저면적 2:1 Multiplexer 설계
김선중(Sun-Jung Kim),범진욱(Jin-Wook Burm) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
A 20Gb/s 2:1 multiplexer(MUX) IC using 0.13㎛ CMOS was designed and fabricated. Inductive peaking technology was used to improve the performance. The designed 4.662nH micro-spiral inductor was 20×20㎛² in size. 2:1 MUX with and without micro spiral inductors were compared. The rise and fall time was improved more than 7.1% and 9.3% using the micro spiral inductors and capacitance cancellation technique for 20Gb/s signal It consumed 35㎽ and voltage output swing was 300㎷p-p at 20Gb/s.
10MHz/77dB 다이내믹 영역을 가진 선형 가변 이득 증폭기
차진엽,여환석,김도형,범진욱,Cha, Jin-Youp,Yeo, Hwan-Seok,Kim, Do-Hyung,Burm, Jin-Wook 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.8
본 논문은 구조물 모니터링을 위한 광섬유 센서 시스템의 수신단 응용을 위한 CMOS 기반의 가변 이득 증폭기 집적회로 설계에 초점을 두고 있다. 차동증폭기와 선형 linear-in-dB 제어기를 사용한 3단 가변 이득 증폭기를 제시하였다. 제안된 가변이득 증폭기는 전류의 비에 의해 증폭기의 이득이 linear-in-dB 하게 조절되는 일반적인 가변 이득 증폭기의 변형된 형태이다. 본 논문에서 제안된 가변 이득 증폭기는 1.5 dB의 간격으로 77 dB의 다이내믹 영역을 가졌다. 이득오차는 77 dB 다이내믹 영역에서 1.5 dB 이하를 얻었다. 동작범위는 10 MHz를 얻었으며, 단일 1.8 V 전압에서 13.8 mW의 전력소모 특성을 보였다. 이 가변 이득 증폭기는 Magnachip 사의 $0.18{\mu}m$ CMOS 공정을 사용하여 구현되었으며, 유효면적은 $430{\mu}m{\times}350{\mu}m$ 이었다. 제안된 가변 이득 증폭기는 구조물 모니터링을 위한 광섬유 센서 시스템의 수신단에 적용이 가능하였다 측정 결과에 따라 제안된 방법은 다이내믹 영역의 증대와 좋은 linear-in-dB 특성 관점에서 유효하였다. CMOS variable gain amplifier (VGA) IC designs for the structure monitoring systems of the telemetries were developed. A three stage cascaded VGA using a differential amplifier and a linear-in-dB controller is presented. A proposed VGA is a modified version of a conventional VGA such that the gain is controlled in a linear-in-dB fashion through the current ratio. The proposed VGA circuit introduced in this paper has a dynamic range of 77 dB with 1.5 dB gain steps. It also achieved a gain error of less than 1.5 dB over 77 dB gain range. The VGA can operate up to 10MHz dissipating 13.8 mW from a single 1.8 V supply. The core area of the VGA fabricated in a Magnachip $0.18{\mu}m$ standard CMOS process was about $430{\mu}m{\times}350{\mu}m$. According to measurement results, we can verify that the proposed method is reasonable with regard to the enhancement of dynamic range and the better linear-in-dB characteristics.
의료기기용 10bit, 125Ks/s Successive Approximation A/D Converter
김재운(Jae-Woon Kim),범진욱(Jin Wook Burm),임신일(Shin-Il Lim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper describes the design of a 10-bit 125 KSample/S Successive Approximation A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b Split Weighted Capacitance Type DAC design and reduce the area of capacitor by 1/15 multiple compared with Binary Weighted Capacitance Type 10-b DAC design. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 114㎼ at the supply voltage of 1.8V with a 0.18㎛um CMOS technology.