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An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring
Hyunbean Yi 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.1
In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-onchip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.
On-Chip Support for NoC-Based SoC Debugging
Hyunbean Yi,Sungju Park,Kundu, Sandip IEEE 2010 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.57 No.7
<P>This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based system-on-chips (SoCs). We present a test wrapper and, a test and debug interface unit. They enable data transfer between a tester/debugger and a core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate test and debug. We also present a novel core debug supporting logic to enable transaction- and scan-based debug operations. The basic operations supported by our scheme include event processing, stop/run/single-step and selective storage of debug information such as current state, time, and debug event indication. This allows internal visibility and control into core operations. Experimental results show that single and multiple stepping through transactions are feasible with moderately low area overhead.</P>
A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains
Yi, Hyunbean,Kundu, Sandip,Cho, Sangwook,Park, Sungju IEEE 2010 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.57 No.7
<P>This brief presents a design-for-debug technique for a system-on-a-chip with multiple clock domains. We describe the debugging limitations that can exist between different clock domains when performing a scan-based debug methodology and then propose a scan cell and debug control logic to address those limitations. The proposed scan cell is designed to hold and shift the current or the previous state and support online debug. The debug control logic optimizes a core test infrastructure such as the IEEE 1500 test wrapper to minimize area overhead.</P>
Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains
Hyunbean Yi,Jaehoon Song,박성주 한국전자통신연구원 2008 ETRI Journal Vol.30 No.3
This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.
An On-Chip Test Clock Control Scheme for Circuit Aging Monitoring
Yi, Hyunbean The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.1
In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. Aging can be monitored by performing a delay test at faster clocks than functional clock in field and checking the current delay state from the test clock frequencies at which the delay test is passed or failed. In this paper, we focus on test clock control scheme for a system-on-chip (SoC) with multiple clock domains. We describe limitations of existing at-speed test clock control methods and present an on-chip faster-than-at-speed test clock control scheme for intra/inter-clock domain test. Experimental results show our simulation results and area analysis. With a simple control scheme, with low area overhead, and without any modification of scan architecture, the proposed method enables faster-than-at-speed test of SoCs with multiple clock domains.
A Scan-Based On-Line Aging Monitoring Scheme
Hyunbean Yi,Tomokazu Yoneda,Michiko Inoue 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.1
In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.
A Scan-Based On-Line Aging Monitoring Scheme
Yi, Hyunbean,Yoneda, Tomokazu,Inoue, Michiko The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.1
In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.
이현빈(Hyunbean Yi),김주섭(Jusub Kim),박성주(Sungju Park),박창원(Changwon Park) 한국정보과학회 2005 한국정보과학회 학술발표논문집 Vol.32 No.1
본 논문은 통신 시스템에서 오류 검출을 위해 널리 사용되고 있는 회로의 병렬 Cyclic Redundancy Check (CRC) 구현을 위한 최적화 알고리즘을 제시한다. 논리 단을 최소로 하면서 가능한 많은 공유 텀을 찾아 매핑 함으로써 속도 및 게이트 수를 줄인다. 본 논문에서는 이더넷의 32비트 CRC를 병렬로 구현하여 성능평가를 하였다. FPGA 및 표준 셀 라이브러리를 이용하여 합성하였으며,기존의 방식에 비해 속도와 면적 모두 향상되었음을 보여준다.
저비용 SoC 테스트를 위한 IEEE 1500 래퍼 및 테스트 제어
이현빈(Hyunbean Yi),김진규(Jinkyu Kim),정태진(Taejin Jung),박성주(Sungju Park) 대한전자공학회 2007 電子工學會論文誌-SD (Semiconductor and devices) Vol.44 No.11
본 논문에서는 저비용 SoC 테스트를 위한 테스트 설계 기술에 대해서 다룬다. IEEE 1500 랩드 코어를 SoC TAP (Test Access Port) 을 통하여 스캔 테스트를 수행하는 방법을 제시하고, 지연고장 테스트를 위한 테스트 클럭 생성회로를 설계한다. TAP의 신호만을 이용하여 SoC 테스트를 수행함으로써 테스트 핀 수를 줄일 수 있고, SoC 내부의 회로를 사용하여 지연고장 테스트를 수행함으로써 저가의 테스트 장비를 사용할 수 있다. 실험을 통하여 제시한 방식의 효율성을 평가하고, 서로 다른 주파수의 클럭을 사용하는 여러 코어의 지연고장 테스트를 동시에 수행 할 수 있음을 확인한다. This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.
IEEE 1500 래퍼를 이용한 효과적인 AMBA 기반 시스템-온-칩 코아 테스트
이현빈(Hyunbean Yi),한주희(Juhee Han),김병진(Byeongjin Kim),박성주(Sungju Park) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.2
본 논문에서는 Advanced Microcontroller Bus Architecture (AMBA) 기반 System-on-Chip (SoC) 테스트를 위한 임베디드 코어 테스트 래퍼를 제시한다. IEEE 1500 과의 호환성을 유지하면서 ARM의 Test Interface Controller (TIC)로도 테스트가 가능한 테스트 래퍼를 설계한다. IEEE 1500 래퍼의 입출력 경계 레지스터를 테스트 패턴 입력과 테스트 결과 출력을 저장하는 임시 레지스터로 활용하고 변형된 테스트 절차를 적용함으로써 Scan In과 Scan Out 뿐만 아니라 PI 인가와 PO 관측도 병행하도록 하여 테스트 시간을 단축시킨다. This paper introduces an embedded core test wrapper for AMBA based System-on-Chip (SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller (TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.