Activator-specific requirements of distinct Mediator proteins

Kim, Taewhan,Kim, Jeongmo,Kwon, Yongjae,Kim, Young-Joon 이화여자대학교 세포신호전달연구센터 2004 고사리 세포신호전달 심포지움 Vol. No.6

Living cells cope with diverse physiological and environmental changes by reprogramming the pattern of gene expression to mount an appropriate biological response. Although distinct sequence-specific transcription factors that bind to particular regulatory elements and enhancers are primarily responsible for this regulation, transcriptional coactivator-corepiessor proteins that allow these factors to transmit signals that affect both chromatin structure and the transcription machinery also add a significant secondary layer to the regulation of gene expression. A number of coactivator complexes have been identified in eukaryotes, and their functions in gene activation at specific promoters have been analyzed, primarily in vitro. However, the mechanism by which these transcriptional coactivators regulate gene expression in living organisms is not well understood. We isolated the Drosophila Mediator complex and showed that it is critical for transcriptional activation in response to diverse activator proteins in vitro. More importantly, we found that Mediator mutant flies exhibit transcriptional defects for a wide range of developmentally regulated genes, validating the requirement for Mediator in gene transcription in vivo. In addition, for transcription of the Drosophila heat shock genes, Mediator is recruited to the promoter region by heat shock transcription factor(HSF) under heat shock conditions. This indicates that Mediator is the primary in vivo activator target that relays regulatory signals from enhancer-bound activators to the basal transcription machinery. However, it is necessary to explore this idea further by examining the interaction of Mediator with many other activator proteins before we accept any generalized view of the mechanism by which Mediator regulates Pol Ⅱ transcription. For this, we tested a number of natural transcriptional activator proteins for their ability to interact with Mediator proteins in vitro. When twenty-five components were tested, these activators required different components for activation each other. Hence each activator appears to depend on distinct binding targets for Mediator recruitment and transcriptional activation. These findings will aid us in our understanding of the mechanisms by which gene-specific cofactors are recruited to promoters for selective transcriptional activation in higher eukaryotes.

Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization

Kim, Taewhan,Kim, Jungeun IEEE 2007 IEEE transactions on computer-aided design of inte Vol.26 No.1

<P>In many embedded systems, particularly those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It has been known that there are high variations in memory-access delays depending on the ways of designing memory configurations and assigning arrays to memories. Furthermore, embedded-DRAM technology that provides efficient access modes is actively being developed, possibly becoming a mainstream in future embedded-system design. In that context, in this paper, the authors propose an effective solution to the problem of (embedded DRAM) memory allocation and mapping in memory-access-code generation with the objective of minimizing the total memory-access time. Specifically, the proposed approach, called memory-access-code optimization (MACCESS-opt), solves the three problems simultaneously: 1) determination of memories; 2) mapping of arrays to memories; and 3) scheduling of memory-access operations, so that the use of DRAM-access modes is maximized while satisfying the storage size constraint of embedded systems. Experimental data on a set of benchmark designs are provided to show the effectiveness of the proposed integrated approach. In short, MACCESS-opt reduces the total memory-access latency by over 18%, from which the authors found that the memory mapping and scheduling techniques in MACCESS-opt contribute about 12% and 6% reductions of the total memory-access latency, respectively</P>

Synthesis and exploration of clock spines

Kim, Youngchan,Kim, Taewhan Institution of Electrical Engineers 2018 IET computers & digital techniques Vol.12 No.5

Task-Level Dynamic Voltage Scaling for Embedded System Design

Taewhan Kim 한국정보과학회 2010 Journal of Computing Science and Engineering Vol.4 No.3

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications in embedded system design. The effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. The penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of tasks to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimization due to the increase of the overhead of transition time and energy. In addition, DVS needs to be carefully applied so that the dynamically varying chip temperature should not exceed a certain threshold because a drastic increase of chip temperature is highly likely to cause system function failure. This paper reviews representative works on the theoretical solutions to DVS problems regarding inter-task DVS, intra-task DVS, voltage transition, and thermal-aware DVS.

Applications of Voltammetry in Lithium Ion Battery Research

Kim, Taewhan,Choi, Woosung,Shin, Heon-Cheol,Choi, Jae-Young,Kim, Ji Man,Park, Min-Sik,Yoon, Won-Sub The Korean Electrochemical Society 2020 Journal of electrochemical science and technology Vol.11 No.1

Li ion battery (LIB) is one of the most remarkable energy storage devices currently available in various applications. With a growing demand for high-performance batteries, the role of electrochemical analysis for batteries, especially, electrode reactions are becoming very important and crucial. Among various analytical methods, cyclic voltammetry (CV) is very versatile and widely used in many fields of electrochemistry. Through CV, it is possible to know electrochemical factors affecting the reaction voltage and reversibility, and furthermore, quantitative analysis on Li⁺ diffusivity as well as intercalation and capacitive reactions, and also anionic redox reaction. However, the explanation or interpretation of the results of CV is often deficient or controversial. In this mini-review, we briefly introduce the principle of cyclic voltammetry and its applications in LIB to bring a better understanding of the electrochemical reaction mechanisms involved in LIB.

조건부 분기를 가진 데이타-흐름 그래프 스케쥴링 알고리즘

김태환(Taewhan Kim) 한국정보과학회 2001 정보과학회논문지 : 시스템 및 이론 Vol.28 No.1·2

이 논문에서는 중첩된 조건부 분기를 가진 데이타-흐름 그래프에 대한 효과적인 스케쥴링 알고리즘을 제안한다. 이러한 그래프의 스케쥴링은 조건부 자원 공유 문제를 추가적으로 고려해야 하기 때문에 상당히 복잡하게 된다. 이 논문은 이를 적절히 해결하기 위한 방법을 제시하고 있는데 그 핵심은 조건부 분기가 있는 데이타-흐름 그래프를 조건부 분기가 없는 동일한 기능의 그래프로 변형시키는데 있다. 이렇게 함으로서, 변형된 그래프에 설계자의 관심에 맞는 기존의 스케쥴링 알고리즘을 선택 적용하여 스케쥴을 얻을 수 있고, 이것에서부터 원래 그래프의 스케쥴을 생성 할 수 있다. 실험 결과로부터 우리는 이러한 접근 방식이 매우 효과적임을 입증한다. An effective scheduling algorithm for dataflow graphs with conditional branches is presented. Since such data-flow graphs entail the problem of conditional resource sharing additionally, the scheduling problem becomes more complicated. To resolve this problem, we propose a new algorithm whose main role is to transform a data-flow graph with conditional branches into a functionally equivalent one that has no conditional branches. A schedule is then obtained for the transformed one by using an existing scheduling algorithm, from which a schedule for the original data-flow graph is obtained. Experimental results show that the proposed approach is quite effective.

엘리트 펜싱 플뢰레 여자 선수 공격기술의 상지와 하지분절 움직임 분석

김태완 ( Taewhan Kim ),최상협 ( Sanghyup Choi ) 한국스포츠정책과학원 2021 체육과학연구 Vol.32 No.3

PURPOSE This study aims to help improve performance by comparing and analyzing the kinematic variables for each upper and lower extremities segment when two groups of players attack the national women’s fencing players in a match situation. METHODS This study divided the movement time, movement time ratio, Fente step length change, angle factor at each event, and velocity factor of the fencing point of a sword at each event into the Olympic medalists’ group (Group A) and the international competition winners group (Group B) during the fencing Marche Fente. An independent t-test was performed for each factor, and the results were compared. RESULTS As a result, the difference between the two groups in movement time was statistically significant in the front of the foot in the velocity factor. However, no statistical significance was found between the two groups in the front angle of the trunk, the elbow angle, and the knee angle. CONCLUSIONS This indicates that group A and group B are both outstanding players with the best performance, so they are similar in the details of the movements except for the very slight difference in time and velocity. Therefore, the average of the result values of the joint angle will be a feedback index for fencing beginners or education subjects who are now starting to fencing. [목적] 본 연구에서는 국가대표 여자 플뢰레선수들을 대상으로 두 그룹의 선수들이 경기 상황에서 공격 시 상지와 하지의 분절(segment)별 메커니즘에 대해 운동학적 변인을 비교 분석하여 경기력향상에 도움을 주고자 한다.[방법] 펜싱 마르쉬 팡트 동작 시 동작수행 시간(구간별 소요시간, 구간별 소요시간 비율), 국면별 보폭 변화, 각 시점별 각도 요인(상지의 몸통전경각, 팔꿈치각, 무릎각), 각 시점별 펜싱 칼끝의 속도 요인(앞발과 뒷발)을 올림픽 메달리스트 그룹(A 그룹)과 국제대회 입상자 그룹(B 그룹)으로 나누어 각 요인별로 독립 t-검정을 실시하여 결과를 비교하였다.[결과] 분석 결과 동작 수행 시간에서 두 그룹 간 차이를 보였고, 속도 요인에서도 앞발에서 통계적으로 유의한 차이를 나타냈다. 하지만 몸통의 전경각, 팔꿈치각, 무릎각에서는 두 그룹 간 통계적 유의점을 찾지 못했다.[결론] 이는 A 그룹과 B 그룹이 모두 최고의 기량을 발휘하는 매우 우수한 선수라는 점에서 매우 근소한 시간과 속도의 차이를 제외한 동작의 디테일한 부분에서는 유사하다는 것을 나타내는 것이다. 따라서 관절 각도의 결과 값의 평균은 펜싱 초보자나 이제 펜싱을 시작하는 교육 대상자들의 피드백 지표가 될 것이고, 이와 더불어 A 그룹의 시간 요인과 속도 요인결과에 대한 수행 목표를 참고하여 훈련을 한다면 매우 우수한 교육 및 경기 결과를 낼 것으로 판단된다.

The development of a team building program for korean curling team

( Youngsook Kim ),( Sanghyuk Park ),( Taewhan Kim ) 한국스포츠정책과학원(구 한국스포츠개발원) 2017 International Journal of Applied Sports Sciences Vol.29 No.2

The purpose of this study was to develop and apply a team building program for a curling team through needs assessment. The participants in this study were 69 high-school, college, professional, and national curling athletes for the needs assessment, 4 sport psychologists and 2 curling experts for verifying the validity of the program, and 5 curling athletes of professional curling teams for the application of the team building program. The needs assessment data were analyzed by inductive content analysis. The team building program was developed based on the results of needs assessment, goal setting of the team building program, and a selection of activities for the team building program. The team building program was applied to five curling players for 7 sessions. Team cohesion, team efficacy, and effective communication were measured two times (i.e., pre and post) to examine the effects of team building intervention. The results of needs assessment indicated interpersonal relationship, communication, and performance were necessary factors for team building. Consequently, goals of the team building program were to improve communication and interpersonal relationships. Team building activities were selected through team building literature review and expert meetings. Secondly, the team building intervention had a positive influence on team cohesion, team efficacy, and communication. These results indicated that team building would positively contribute to team factors and team performance.

네트워크 - 플로우 방법을 기반으로 한 통합적 데이타 - 경로 합성 알고리즘

김태환(Taewhan Kim) 한국정보과학회 2000 정보과학회논문지 : 시스템 및 이론 Vol.27 No.12

이 논문은 상위 단계 데이타-경로 합성에서 연산 스케쥴링과 자원 할당 및 배정을 동시에 고려한 통합적 접근 방법을 제시한다. 제안한 방법은 스케쥴링 되어있지 않은 데이타-플로우 그래프에 대해서 수행에 필요한 총 clock 스텝 수와 필요한 회로 면적을 동시에 최소화하는 데이타-경로 생성에 특징이 있다. 일반적으로, 연결선의 결정이 합성의 마지막 단계에서 이루어지는 기존의 방법과는 다르게, 우리의 접근 방법은 연산 스케쥴링과 연산의 연산 모듈 배정 그리고 변수의 레지스터 배정 작업을 동시에 수행하여 추가적인 연결선의 수를 매 clock 스텝마다 최적화(optimal) 시킨다. 본 논문은, 이 문제를 최소-비용의 최대-플로우 문제로 변형하여 minimum cost augmentation 방법으로 polynomial time안에 해결하는 알고리즘을 제안한다. We present an integrated approach to the problems of the scheduling, allocation (register and interconnections), and binding in high-level synthesis. Our algorithm synthesizes a data path from an unscheduled dataflow graph with an objective of minimizing both the number of control steps and total design area. Unlike most of the prior approaches in which interconnections are determined only in the final step of the synthesis process, in our approach, scheduling of operations, binding of operations to functional units, and binding of variables to registers are performed simultaneously so that interconnections are determined optimally for each clock step. The problem is formulated as a minimum cost maximum flow problem in a network which can be solved in polynomial time using the minimum cost augmentation method.

VLSI 설계에서 캐리-세이브 가산기를 이용한 설계 블록들 간의 최적화

김태환(Taewhan Kim),엄준형(Junhyung Um) 한국정보과학회 1999 정보과학회논문지 : 시스템 및 이론 Vol.26 No.5

캐리-세이브 가산기(CSA)는 실제 산업체에서 회로를 설계할 때 연산 수식의 계산을 빠르게 처리하기 위해 가장 많이 사용되는 구성 요소들 가운데 하나이다. [3]의 자료에 의하면, 실제 회로 설계에서 나오는 전형적인 연산식에 CSA를 이용했을 때 그렇지 않은 경우보다 최대 54%의 연산 처리 속도와 42%의 회로 면적 향상을 갖는다고 보고하고 있다. 그러나, 이는 그 연산식이 하나의 설계 블록(sub-design)에 포함되어 있다는 전제하에 도출된 것이었다. 회로 설계 규모와 복잡도가 큰 응용이 많아지는 상황에서 설계 블록 단위의 계층적(level of hierarchy) 설계는 필수적인 추세이므로, CSA를 이용한 회로 최적화를 실현하기 위해서는 설계 블록들 간에 걸쳐 있는 연산식에 대한 CSA 최적화 또한 매우 중요한 문제이다. 이를 해결하기 위해 이 논문에서는 auxiliary port라는 개념을 이용하여 설계 블록들간의 연산식에 대한 CSA 최적화 방법을 제안한다. 실제 실험에서 우리가 제안한 기법은 회로의 전체적인 영역에 걸쳐 CSA를 적용하는데 매우 효과적이었으며, 이 기법을 적용하지 않고 얻은 CSA 최적화 회로와 비교했을 때 회로에서의 연산식 계산 속도와 그 회로 면적이 상당히 향상되었음을 확인하였다. Carry-gave-adder (CSA) is the most often used type of component in implementing a fast computation of arithmetics in industry. It was reported in [3] that typical arithmetic computations found in industry designs were optimized using CSAs, producing designs with upto 54% faster timing and 42% smaller area. However, These results are based on the assumption that the arithmetic expression to be optimized must entirely be placed in one sub-design. As the demand of applications with high complexity of circuits increases, CSA optimization across boundary of design hierarchy is becoming more important. In this paper, we present an effective algorithm to solve the problem of CSA optimization across boundary of design hierarchy. Specifically, we present an optimization technique using a concept of auxiliary ports to solve the problem of CSA transformation for operation in different levels of design hierarchy. In fact, our experimentations indicate that our algorithm incorporating the concept was able to extensively utilize CSAs throughout the whole circuit, and as a result, it produces designs with significantly faster timing and less area.