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A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
Taegeun Yoo,Hong Chang Yeoh,Yun-Hwan Jung,Seong-Jin Cho,Yong Sin Kim,Sung-Mo Kang,Kwang-Hyun Baek IEEE 2014 IEEE journal of solid-state circuits Vol.49 No.12
<P>This paper presents a direct digital frequency synthesizer (DDFS) based on the nonlinear DAC with a maximum operating frequency of 2 GHz. This work proposes three design methods to enhance the performance of a DDFS. First, a multi-level momentarily activated bias is proposed to reduce power dissipation in the phase accumulator. Second, a coarse phase-based consecutive fine amplitude grouping scheme is presented to reduce hardware complexity and power consumption in the digital decoder. Third, the mixed-wave conversion topology in the nonlinear DAC is proposed to improve the output spectral purity. The DDFS with 9 bit amplitude resolution is capable of producing a minimum spurious-free dynamic range (SFDR) of 55.1 dBc up to Nyquist frequency at the clock frequency of 2 GHz. The prototype DDFS is fabricated in a 55-nm CMOS. It occupies an active area of 0.1 mm 2 with a total power dissipation of 130 mW. The figure of merit of this DDFS is 8944 GHz · 2 (SFDR/6) /W.</P>
유태근 ( Taegeun Yoo ),홍윤아 ( Yoona Hong ),김명준 ( Minwoo Hwangbo ),황보민우 ( Myeoungjun Kim ),강윤희 ( Yunhee Kang ),강명주 ( Myungju Kang ) 한국정보처리학회 2021 한국정보처리학회 학술대회논문집 Vol.28 No.2
이 논문에서는 다매체를 사용하여 데이터를 수집한 후 기계학습을 통해 분석하고 주어진 상황에 대응하기 위한 시스템의 개발을 기술한다. 개발 시스템은 센서데이터 수집부, 상황인지 및 상황대응부로 이루어지며, 아두이노와 라즈베리파이를 사용하여 구성한다. 구성된 시스템은 영상 카메라 및 온습도을 포함한 다수의 센서를 사용하여 환경정보를 수집한 후 수집자료를 전처리하고 주어진 상황을 인지하여 상황에 가장 적절하다고 판단되는 대응을 안내하도록 기능을 구성하였다. 상황인지를 위해서는 기계학습 알고리즘으로 의사결정트리를 사용하였으며 100%의 상황인지 정확률을 갖는다.
Pham, Ngoc-Son,Yoo, Taegeun,Kim, Tony Tae-Hyoung,Lee, Chan-Gun,Baek, Kwang-Hyun IEEE 2018 IEEE TRANSACTIONS ON POWER ELECTRONICS - Vol.33 No.11
<P>A single-inductor multiple-output (SIMO) dc–dc converter with output-voltage-aware charge control (OVACC) is presented in this paper. The OVACC scheme reduces the cross regulation by computing the total energy required by all outputs to extract exactly the same amount of energy from the input. Moreover, the proposed design also extends the load capability range of the SIMO converter by supporting the operation in both continuous conduction mode and discontinuous conduction mode while boosting the overall power efficiency. The proposed SIMO (five outputs) dc–dc converter has been implemented in a 0.18 <I>μ</I>m 1P6M CMOS process. Measurement results show that the best cross regulation is 0.016 mV/mA when the output current of 250 mA abruptly changes. And no cross regulation is observed when the first output current changes 150 mA, the second output current changes 160 mA, the third and fourth output currents change 180 mA, and the last output current changes 250 mA. Also, the measured peak power efficiency is 86%.</P>
A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations
Yun, Jaecheol,Jung, Yun-Hwan,Yoo, Taegeun,Hong, Yohan,Kim, Ju Eon,Yoon, Dong-Hyun,Lee, Sung-Min,Jo, Youngkwon,Kim, Yong Sin,Baek, Kwang-Hyun The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.3
A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-nm CMOS technology. Measured results show that the worst SFDR performances are 60 dBc and 55 dBc in the 1st and 2nd Nyquist bands, respectively, when operating at 650 MHz clock frequency. The total power consumption is 64 mW, and the active area occupies $0.25mm^2$.
Energy-efficient Spread Second Capacitor Capacitive DAC for SAR ADC
Ju Eon Kim,Sung-Min Lee,Taegeun Yoo,Yong-Jun Jo,Kwang-Hyun Baek 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
An energy-efficient capacitive digital-to-analog converter (C-DAC) switching with spread second capacitor is proposed for low power successive approximation register analog-to-digital converters (SAR ADCs). In the proposed spread second capacitor capacitive digital-to-analog converter (SSC C-DAC), all capacitors except the most significant bit (MSB) capacitor are switched after the second bit decision. Because the burden of the second capacitor switching is shared with all capacitors except the MSB capacitor, the number of unit capacitors and the burden of driving VCM are reduced. The proposed SSC C-DAC achieves 98.1% more efficient switching energy and can be comprised of the number of quarter unit capacitors, contrary to that in conventional schemes. The fabricated differential-type SAR ADC with SSC C-DAC has a 10-bit resolution and 10-MS/s sampling speed in 0.18-μm CMOS process. The test results show a SFDR of 60.9 dBc, a SINAD of 53.1 dB and an ENOB of 8.5 bit.
Jung, Dong-Kyu,Jung, Yun-Hwan,Yoo, Taegeun,Yoon, Dong-Hyun,Jung, Bo-Yun,Kim, Tony Tae-Hyoung,Baek, Kwang-Hyun IEEE 2018 IEEE transactions on circuits and systems. a publi Vol.65 No.11
<P>This paper presents a 12-bit multi-channel resistor–resistor-string digital-to-analog converter (RRDAC) using a shared R-string scheme for an area efficient display source driver. The proposed scheme relaxes the required equivalent resistance value of R-string of each channel by sharing a channel R-string that is simultaneously connected to the same tap of a global R-string. Thus, the overall DAC size can further be minimized while maintaining the same accuracy. That is, if the proposed scheme is implemented with the same size as the conventional RRDAC, higher accuracy can also be achieved. For the verification of shared resistor string scheme, a 12-bit RRDAC was fabricated using 0.35- <TEX>$\mu$</TEX>m standard CMOS technology. Compared with the conventional RRDAC, the proposed design showed a 15% reduction in size, a DNL of 0.49 LSB and an output voltage deviation of 9. 3mV for eight different chips. Also, the area per channel was 0.0465 mm<SUP>2</SUP>.</P>
A Return-to-zero DAC with Tri-state Switching Scheme for Multiple Nyquist Operations
Jaecheol Yun,Yun-Hwan Jung,Taegeun Yoo,Yohan Hong,Ju Eon Kim,Dong-Hyun Yoon,Sung-Min Lee,Youngkwon Jo,Yong Sin Kim,Kwang-Hyun Baek 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.3
A return-to-zero (RZ) digital-to-analog converter (DAC) with a tri-state switching scheme is proposed in this paper. The proposed scheme provides a triple weight output for RZ operation by using a conventional differential current switch and simple pseudo-differential F/Fs. The RZ function is realized with only two additional transistors in each F/F cell, which results in a power dissipation increase of less than 5%. To verify the performance of the proposed method, a 10-bit RZ DAC is fabricated using standard 180-㎚ CMOS technology. Measured results show that the worst SFDR performances are 60 ㏈c and 55 ㏈c in the 1st and 2nd Nyquist bands, respectively, when operating at 650 ㎒ clock frequency. The total power consumption is 64 ㎽, and the active area occupies 0.25 ㎟.