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Power-aware 32Bit SIMSD Path Architecture Using Single/Parallel Mode Bit and 2 Step Gating Technique
Yil Suk Yang,Tae Moom Roh,Dae Woo Lee,Nae Soo Cho,Woo H. Kwon,Jongdae Kim 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper describes 32bit parallel data path architecture for high-energy efficiency. We apply a parallel architecture, a 2 step gating technique and single/parallel mode bit in order to high energy efficiency. The energy efficiency of the proposed 32bit SIMSD (Single Instruction Multiple/Single Data) path architecture can improve about 20% than that of the conventional 32bit parallel data architecture without using 2 step gating technique.