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CMOS Delta-Sigma Frequency Synthesizer with a New Frequency Divider and a Simpli ed MASH Structure
Soo-HwanKim,Min-SunKeel,Ki-WonLee,Suk-KiKim,Shin-IlLim 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.41 No.6
This paper describes a CMOS implementation of a fractional-N frequency synthesizer adopting a new frequency divider and a new simplified 3-stage MASH (multistage noise shaping) delta-sigma modulator. All functional blocks, except for the low-pass filter (LPF), are integrated on a chip. A simple frequency divider architecture with a digital comparator and a `modulus mapping circuit' in a delta-sigma modulator is suggested for a lower hardware complexity and less power consumption. The proposed fractional-N frequency synthesizer shows a rapid switching time of 2.8 $\mu$s at a 60-MHz frequency step with inherent high reference frequency and a wide loop bandwidth. The tuning range of the voltage-controlled oscillator (VCO) is 1.6$\sim$2.1 GHz in the measured results. The measured VCO phase noise is as low as $-$110.27 dBc/Hz at a 600-kHz offset and $-$122.99 dBc/Hz at a 7.5-MHz offset. The measured fractional spur level is $-$101.6 dBc. The total power consumption is 20.2 mW with a 2.5 V single power supply. The synthesizer is implemented in a 0.25-$\mu$m standard CMOS process (1-poly, 5-metal) and occupies an active area of 760$\times$1280 $\mu$m.