Survey of Low-Power Electric Vehicles: A Design Automation Perspective

Chang, Naehyuck,Faruque, Mohammad Al,Shao, Zili,Xue, Chun Jason,Chen, Yiran,Baek, Donkyu IEEE Computer Society 2018 IEEE design & test Vol.35 No.6

<P>The survey of the guest editors provides a comprehensive introduction to the design process of electric vehicles. Relevant topics such as the modeling of efficiency of the propulsion engine, optimization of the propulsion engine, runtime driving management, battery systems, and charging are introduced and provide the necessary knowledge to understand state-of-the-art research of this special issue. —<I>Jörg Henkel, Editor in Chief</I></P>

상위 수준에서 행해지는 전력 소모 절감의 원리, 도구와 방법

장래혁(Naehyuck Chang) 한국정보과학회 2002 정보과학회지 Vol.20 No.10

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

Jaehyun Park,Donghwa Shin,Naehyuck Chang,Hyung Gyu Lee 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.6

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

행렬구조 메모리 참조표를 사용한 페트리네트 제어기의 하드웨어 구현

장래혁(Naehyuck Chang),정승권(Seungkweon Jeong),권욱현(Wook Hyun Kwon) 제어로봇시스템학회 1998 제어·로봇·시스템학회 논문지 Vol.4 No.2

Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM

Park, Jaehyun,Shin, Donghwa,Chang, Naehyuck,Lee, Hyung Gyu The Institute of Electronics and Information Engin 2014 Journal of semiconductor technology and science Vol.14 No.6

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interface. In this paper, we propose address phase skipping by reforming the way of interfacing with LPDDR2-NVM. To verify effectiveness and functionality, we also develop a system-level prototype that includes our customized LPDDR2-NVM controller and commercial PCM devices. Extensive simulations and measurements demonstrate up to a 3.6% memory access time reduction for commercial PCM devices and a 31.7% reduction with optimistic parameters of the PCM research prototypes in industries.

병렬 컴퓨터를 위한 저지연 프로그램형 조견표 경로지정 엔진

장래혁(Naehyuck Chang) 한국정보과학회 2000 정보과학회 컴퓨팅의 실제 논문지 Vol.6 No.2

병렬 컴퓨터의 메시지 전달에서 응용에 관계없이 일반적으로 우수한 경로 지정 및 스위칭 정책은 존재하지 않으므로, 사용자가 응용에 따라서 정책을 변경할 수 있게 하는 것이 바람직하다. 본 논문에서는 마이크로프로세서 구조에 기초한 경로 지정 엔진과는 달리, 성능의 감소 없이 융통성 있는 경로지정과 스위칭 기능을 수행할 수 있는 조견표(look-up table) 경로 지정 엔진의 구현에 대하여 기술한다. 제안된 경로 지정 엔진은 조견표의 내용을 바꿈으로써 웜홀(wormhole), 가상 컷스루우(virtual cut-through) 및 패킷 스위칭(packet switching) 등은 물론, 다양한 경로 지정 알고리즘의 혼성(hybride) 스위칭을 구현할 수 있다. 경로 지정 엔진의 조견표는 파이프라인 구조로 되어 있어, 하나의 플릿(flit) 정도의 저 지연을 가지므로, 단일 경로 지정 및 스위칭 정책을 하드와이어(hardwired)로 구현한 경우 보다 큰 성능의 감소 없이 다중의 경로 지정 동작을 중첩할 수 있다. 제안된 4개의 파이프 라인단은 해저드(hazard)를 일으키지 않으므로, 고 비용의 포워딩(forwarding) 회로가 필요 없다. 경로 지정 엔진은 시간공유의 컷스루우 버스나 크로스바(crossbar) 스위치를 갖는 단일 경로로 되어 있는 4개의 물리적 경로를 수용할 수 있다. 제안된 경로 지정 엔진은 Xilinx 4000XL 시리즈 FPGA를 사용하여 구현되었다. Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.

SAVE : 소프트웨어 모델을 사용한 효율적인 실시간 하드웨어 검증 시스템

장래혁(Naehyuck Chang),성현중(Hyun Joong Sung),전주식(Chu Shik Jhon) 한국정보과학회 1998 한국정보과학회 학술발표논문집 Vol.25 No.1A

FPGA를 사용한 시제품 제작은 ASIC을 사용하여 하드웨어를 구현하는 경우에, 설계 오류로 인한 비용 및 개발기간 증가를 피하기 위하여, 중간 검증 단계로서 많이 사용된다. 그렇지만 ASIC에 비하여 상대적으로 긴 FPGA의 전달 지연으로 인하여, 실제 운용 환경에서 FPGA로 구현된 시제품의 검증을 수행하기 어려운 경우가 흔희 존재한다. 본 논문에서는 이러한 문제를 해결하기 위하여, FPGA를 사용한 중간 단계의 시제품을 효과적이며 정확하게 검증하는 방법을 제공하기 위해 SAVE라는 시스템을 소개한다. 본 논문에서 제안한 검증 시스템은 실제 환경 대신에 소프트웨어 모델을 사용하나, 별도의 하드웨어의 도움을 받아 이를 FPGA 시제품과 인터페이스하여 검증한다. 일반 소프트웨어 검증 환경과는 달리, 본 시스템은 실시간으로 FPGA 시제품을 검증할 수 있으나, 하드웨어 모델기와는 달리 복잡도가 매우 낮다. 본 논문에서는 검증 시스템의 구조 및 하드웨어 구현과 논리 모델을 사용한 검증 데이터의 효과적인 재구성 방법 및 파이프라인 기능의 지원 등을 다룬다.

Build Your Own EV: A Rapid Energy-Aware Synthesis of Electric Vehicles

Baek, Donkyu,Chang, Naehyuck,Kim, Jaemin IEEE Computer Society 2019 IEEE design & test Vol.36 No.1

<P>Electric vehicles (EVs) represent a quantum leap towards addressing climate-change effects and building a more sustainable environment. This article provides a comprehensive overview of the EV benefits, summarizes the main challenges in designing EVs, and describes a pioneering design automation inspired framework for rapid energy-aware electric vehicle synthesis. The opportunities for future work stimulated by these rigorous research efforts are endless.—Paul Bogdan, University of Southern California</P>

Compressed On-Chip Framebuffer Cache for Low-Power Display Systems

Baek, Donkyu,Chang, Naehyuck,Shin, Donghwa IEEE 2017 IEEE transactions on very large scale integration Vol.25 No.4

<P>A framebuffer memory is data storage for the displayed image, which is one of the major power consumers in display systems. This paper proposes a power reduction technique for the on-chip framebuffer cache (FBC) performing a compressed image data management. The proposed architecture stores the compressed image data in the on-chip FBC, and the display controller decompresses the image data on the fly and sends it to the liquid crystal display panel. The compression and decompression processes incur additional power consumption but achieve lower system-wide power consumption. We implement the proposed architecture in a field-programmable gate array platform to confirm power saving by actual measurement. Experiments demonstrate that the proposed on-chip FBC significantly reduces the number of the off-chip framebuffer memory accesses and saves a large portion of the system-wide power consumption accordingly.</P>

Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time

Baek, Donkyu,Chang, Naehyuck IEEE 2019 IEEE transactions on very large scale integration Vol.27 No.3

<P>Installation of a large-capacity battery pack is a straightforward method to extend the range of battery electric vehicles (BEV or all-electric vehicles). However, at the same time, a large-capacity battery pack not only occupies a big space but also significantly increases the vehicle weight, which directly impacts the fuel economy and vehicle performance. This implies that increasing the battery capacity has an obvious limitation in extending the EV range. In this paper, we introduce a system-level framework to extend the range of BEV with the consideration of the vehicle dynamics, electric powertrain characteristics, road slopes, payload, and regenerative braking. This paper particularly takes into account driving time so that the resultant BEV power management does not impractically slow down the vehicle velocity. The BEV power management framework derives energy-aware velocity planning, i.e., a desirable instantaneous velocity at each distance step (or at each time instant). The major technical contributions of this paper compared with the previous work include: 1) practically applicable velocity planning for production BEVs from superb BEV power model fidelity; 2) new performance metrics to consider both driving energy and driving time: energy-delay product (EDP), energy-square-delay product, and energy-cubic-delay product; 3) heuristics to derive EDP-aware velocity planning; 4) comparative analysis of the velocity planning between BEV and internal combustion engine vehicles; and 5) analysis of the model fidelity impact on the energy-aware velocity planning. The proposed method results in up to a 46.2% improvement of the EDP compared with the least-energy constant velocity driving.</P>