都市街路의 遲滯度推定에 관한 硏究

임채문,권강훈,이주호,김태형 대구대학교 과학기술연구소 2001 科學技術硏究 Vol.8 No.1

This study suggested input variables whose effects have been considered by adjusting various input variables in the TRANSYT-7F and NETSIM, the Simulation programs employed in calculating the delay time at street sections. The results can be summarized as follow. 1. Among the input variables in the TRANSYT-7F needed to calculate the delay time at street sections, the excluded are those which effect the most on time delay, such as bus stops, pedestrian crossings and on/off ramps. Among the input variables the most affecting factors are Saturation flow rate and time delay whose suggested quotients are well summarized in the text of this study. 2. There are variables which affect the change of time delay in the NETSIM, such as bus stop, pedestrian crossing, bus appearance period, and departure time delay. This study did the Simulation program using those variables except pedestrian crossing because, as the result of the correlation analysis suggests, there is a strong correlation between bus stop and pedestrian crossing. In this study, the survey had been done in the morning and afternoon except the Peak time, so heavily congested sections were excluded. And both sides of three street sections were surveyed. Therefore, there should be further studies on heavily congested situations and many other street sections.

MgO 버퍼층을 이용한 PZT 박막의 형성 및 특성 평가

김지미,전호승,강재경,최형봉,김철주 서울시립대학교정보기술연구소 2001 정보기술연구소 논문집 Vol.3 No.-

In this paper, we fabricated the MgO layer by sol-gel method and estimated possibility as a buffer layer for ferroelectric such as PZT. MgO(Magnesium Oxide) proposed as buffer layer of ferroelectric is already for much used as buffer layer in optic technology. There are many formation methods of MgO layer, but in this study, we selected the sol-gel method which is easy to control the content of material and possible for fabrication of uniform layer, then we formed thin layer through the composition of MgO and PZT solution, spin coating and annealing. To estimate the possibility as buffer layer about ferroelectric layer, we analyzed the physical and electrical characteristics about PZT on MgO layer.By SEM, AFM and XRD analysis, we could know facts that the surface condition of PZT on MgO was relatively smooth and the crystal orientation of PZT was enhanced by MgO layer. Due to the measurements of P-V, C-V and I-V characteristics of PZT/MgO capacitor structure, the polarization, fatigue and breakdown properties of PZT on MgO were much improved than those of PZT without MgO layer. Also, in MFIS structure, the PZT on MgO showed the stable memory property. These results could be compared to those of MgO buffer layer formed by sputtering, so, if studies about the composition of MgO solution and the formation of MgO layer are executed continuously, the fabrication process of MgO layer by sol-gel method can be applied as the process for buffer layer of ferroelectric.

The toxic effect of dietary arsenic exposure on bioaccumulation and antioxidant response in starry flounder, Platichthys stellatus

Ju-Hyeong Lee,Young-Bin Yu,Jae-Ho Choi,Hyeok-Chan Jung,Ji-Eun Kim,Bitsolyeulednkaorem Kim,Ju-Chan Kang 한국수산과학회 양식분과 2021 한국수산과학회 양식분과 학술대회 Vol.2021 No.4

싱글숏 멀티박스 검출기에서 객체 검출을 위한 가속 회로 인지형 가지치기 기반 합성곱 신경망 기법

Kang, Hyeong-Ju 한국정보통신학회 2020 한국정보통신학회논문지 Vol.24 No.1

Convolutional neural networks (CNNs) show high performance in computer vision tasks including object detection, but a lot of weight storage and computation is required. In this paper, a pruning scheme is applied to CNNs for object detection, which can remove much amount of weights with a negligible performance degradation. Contrary to the previous ones, the pruning scheme applied in this paper considers the base accelerator architecture. With the consideration, the pruned CNNs can be efficiently performed on an ASIC or FPGA accelerator. Even with the constrained pruning, the resulting CNN shows a negligible degradation of detection performance, less-than-1% point degradation of mAP on VOD0712 test set. With the proposed scheme, CNNs can be applied to objection dtection efficiently.

CNN에서 입력 최댓값을 이용한 SoftMax 연산 기법

Kang, Hyeong-Ju 한국정보통신학회 2022 한국해양정보통신학회논문지 Vol.26 No.2

A convolutional neural network(CNN) is widely used in the computer vision tasks, but its computing power requirement needs a design of a special circuit. Most of the computations in a CNN can be implemented efficiently in a digital circuit, but the SoftMax layer has operations unsuitable for circuit implementation, which are exponential and logarithmic functions. This paper proposes a new method to integrate the exponential and logarithmic tables of the conventional circuits into a single table. The proposed structure accesses a look-up table (LUT) only with a few maximum values, and the LUT has the result value directly. Our proposed method significantly reduces the space complexity of the SoftMax layer circuit implementation. But our resulting circuit is comparable to the original baseline with small degradation in precision.

Low-complexity twiddle factor generation for FFT processor

Kang, Hyeong-Ju,Lee, Jong-Yeol,Kim, Ji-Hoon Institution of Electrical Engineers 2013 Electronics letters Vol.49 No.23

Low-Power Time Deinterleaver for ISDB-T Receiver

Hyeong-Ju Kang,Byung-Do Yang IEEE 2012 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.59 No.10

<P>A time deinterleaver structure for Terrestrial Integrated Services Digital Broadcasting (ISDB-T) is presented to reduce power consumption in synchronous dynamic random-access memory (SDRAM). ISDB-T exploits long time interleaving, which requires many long delay buffers at the deinterleaving of the receiver. The conventional single-pointer structure reduces the number of the pointer registers, but it shows inefficiency with SDRAM. The proposed structure allocates the delay buffers appropriately for reducing the number of SDRAM accesses and row activations and, as a result, the SDRAM power consumption. Experimental result shows that SDRAM power consumption is reduced by 24%.</P>

Area-Efficient Prefilter Architecture for a CDMA Receiver

Hyeong-Ju Kang,Seung Jae Lee,Byung-Do Yang IEEE 2011 IEEE transactions on circuits and systems. a publi Vol.58 No.4

<P>This brief proposes an area-efficient memory-based prefilter delay line structure. A prefilter-rake chip-level equalizer is used in a code-division multiple-access receiver to deal with multiple-access interference. A prefilter, which functions as an adaptive filter, has a sparsity property, where the number of taps with nonzero coefficients is much smaller than the number of whole taps. On the basis of the sparsity property, this brief shows how a memory device can be a reasonable candidate for a prefilter delay line. After proposing a scheme to reduce the area of the memory-based delay line, this brief shows that the proposed structure provides less area than a conventional register-based structure in typical industrial cases.</P>

SAT-based unbounded symbolic model checking

Kang, Hyeong-Ju,Park, In-Cheol IEEE 2005 IEEE transactions on computer-aided design of inte Vol.24 No.2

This paper describes a Boolean satisfiability checking (SAT)-based unbounded symbolic model-checking algorithm. The conjunctive normal form is used to represent sets of states and transition relation. A logical operation on state sets is implemented as an operation on conjunctive normal form formulas. A satisfy-all procedure is proposed to compute the existential quantification required in obtaining the preimage and fix point. The proposed satisfy-all procedure is implemented by modifying a SAT procedure to generate all the satisfying assignments of the input formula, which is based on new efficient techniques such as line justification to make an assignment covering more search space, excluding clause management, and two-level logic minimization to compress the set of found assignments. In addition, a cache table is introduced into the satisfy-all procedure. It is a difficult problem for a satisfy-all procedure to detect the case that a previous result can be reused. This paper shows that the case can be detected by comparing sets of undetermined variables and clauses. Experimental results show that the proposed algorithm can check more circuits than binary decision diagram-based and previous SAT-based model-checking algorithms.

Low complexity twiddle factor multiplication with ROM partitioning in FFT processor

Kang, Hyeong-Ju,Yang, Byung-Do,Lee, Jong-Yeol IET 2013 Electronics letters Vol.49 No.9

<P>Proposed is a low-complexity twiddle factor multiplication structure for fast Fourier transform (FFT). In an FFT implementation, the twiddle factor multiplication requires a large ROM to store the twiddle factors. In the proposed structure, the ROM is partitioned into two small ROMs, whose sum of areas is much smaller than that of the original ROM. The proposed structure requires an additional multiplier, but the multiplier is shown to be small in the experimental results. The results show that the proposed structure reduces the area of the twiddle factor multiplication by around 30% with a marginal degradation in SQNR performance.</P>