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RISS 인기검색어
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- 저자 : Injae Yoo (검색결과 20 건)
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Yoo, Injae,Jo, Jihyuck,Ju, Youngjin,Park, In-Cheol The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.5
This paper proposes an Ethernet-based in-vehicle control network and its hardware realization. Since modern premium-class vehicles contain nearly a hundred electronic control units (ECUs), multiple control networks needed for the ECUs become considerably complex. In order to reduce the network complexity, the proposed network connects the ECUs by employing an Ethernet-based unidirectional ring topology. In addition, a new Ethernet media access controller (MAC) is proposed to automatically relay mismatched frames. As a result, the proposed ring network can be constructed without any switching device. A hardware platform employing the proposed MAC as a network controller is implemented on a field programmable gate array to evaluate the realistic performance of the proposed network. Experimental results show that the proposed MAC increases the communication speed by 123%. Moreover, the performance of the proposed network with a large number of ECU nodes is evaluated using the OMNET++ simulation tool, which shows that the proposed network provides the ECUs with much higher communication speed than the conventional CAN and FlexRay do.
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Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks
Yoo, Injae,Park, In-Cheol IEEE 2017 IEEE transactions on circuits and systems. a publi Vol.64 No.9
<P>This brief proposes a low-power low-density parity check convolutional code (LDPC-CC) decoder that is fully compatible with the IEEE 1901 standard. The proposed architecture merges multiple memory banks into one to make it consume much less power than the conventional architecture. Memory operations conducted by all the unit processors are synchronized in the proposed decoder to merge the memory and avoid any possible data hazard. The data hazard happens when a unit processor tries to read a log-likelihood ratio before a different processor updates it, degrading the error-correcting performance. Memory-access patterns appearing in a memory-based LDPC-CC decoder are formulated to determine the size of a sliding window adequate for decoding. Experimental results show that the decoding architecture employing the merged memory and the proper window size reduces the power consumption by up to 40% compared to the conventional architecture that employs multiple memory banks.</P>
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Injae Yoo,Jihyuck Jo,Youngjin Ju,In-Cheol Park 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.5
This paper proposes an Ethernet-based invehicle control network and its hardware realization. Since modern premium-class vehicles contain nearly a hundred electronic control units (ECUs), multiple control networks needed for the ECUs become considerably complex. In order to reduce the network complexity, the proposed network connects the ECUs by employing an Ethernet-based unidirectional ring topology. In addition, a new Ethernet media access controller (MAC) is proposed to automatically relay mismatched frames. As a result, the proposed ring network can be constructed without any switching device. A hardware platform employing the proposed MAC as a network controller is implemented on a field programmable gate array to evaluate the realistic performance of the proposed network. Experimental results show that the proposed MAC increases the communication speed by 123%. Moreover, the performance of the proposed network with a large number of ECU nodes is evaluated using the OMNET++ simulation tool, which shows that the proposed network provides the ECUs with much higher communication speed than the conventional CAN and FlexRay do.
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Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders
Injae Yoo,Bongjin Kim,In-Cheol Park IEEE 2014 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.61 No.9
<P>This paper proposes a novel decoding algorithm to enhance the throughput of turbo decoding in LTE-Advanced systems and its hardware realization. The proposed method completely removes the undesired phase-switching latency by partially overlapping in-ordered and interleaved decoding phases, and as a result, achieves a significant increase of decoding throughput. Moreover, the algorithm does not degrade error-correcting performance for high-rate codes which are essential to achieve the maximum data rate of LTE-Advanced systems. The proposed method called tail-overlapped decoding can be easily applied to the conventional parallel decoding architecture designed for standardized communication systems. In addition, a new structure for the extrinsic information memory is proposed to eliminate memory contentions. A 3GPP LTE-Advanced turbo decoder supporting both decoding methods is implemented in 0.13 μm CMOS technology to show the effectiveness of the proposed algorithm. The decoder exhibits a decoding rate greater than 1Gbps with six iterations, meeting the peak data rate of the LTE-Advanced standard with much less hardware complexity than those of the previous works.</P>
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Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders
Injae Yoo,Bongjin Kim,In-Cheol Park IEEE 2015 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.62 No.12
<P>In this paper, a reverse rate matching method is presented for LTE-Advanced turbo decoders. In LTE-Advanced systems, the turbo codes are highly punctured to achieve high data rate when the channel is reliable. In that case, since only a small part of the input frame memory contains meaningful data, accessing all entries of the memory is redundant. To reduce the meaningless accesses, the proposed reverse rate matching method evaluates whether each code bit is punctured or not. As a result, more than 30% of the power consumed in accessing the input memory can be saved when the code rate is high. Furthermore, a low-complexity hardware architecture realizing the proposed method is presented for parallel-SISO decoding. By making use of a specific relationship resident in parallel input indexes, the hardware complexity of the reverse rate matching unit is reduced by 44%.</P>
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비소세포폐암환자에서 백금착화합물을 포함한 항암화학요법의 비교
신은정,유순호,이병구,손인자,이숙향 한국병원약사회 2001 병원약사회지 Vol.18 No.3
Non-small cell lung cancer (NSCLC) remains the leading cause of cancer related death and 5-year survival rate is approximately 10-15%. Platinum-based chemotherapy has been demonstrated to improve survival in advanced NSCLC. Platinum-based paclitaxel and gemcitabine combination therapy considered moderately active regimen in patients with advanced NSCLC and warrants comparison with existing Platinum-based regimen in randomized trial. The aim of this study was to evaluate toxicity and efficacy of Platinum-based paclitaxel and gemcitabine combination therapy. The medical charts of fifty-six patients with NSCLC, who met selection criteria from January 2000 to March 2001, were reviewed retrospectively. They received one of three regimens greater than 2 cycles up to 7 cycles; paclitaxel (140㎎/㎡) and cisplatin (60㎎/㎡), paclitaxel (120㎎/㎡) and carboplatin (300㎎/㎡), gemcitabine (1000㎎/㎡) and cisplatin (60㎎/㎡). Data collection and analysis included baseline characteristics, hematologic and non-hematologic toxicity profiles according to WHO toxicity criteria and overall response according to clinician's opinion on basis of clinical results. As results, WHO grade above 2 hematologic toxicity occurred high in gemcitabine/cisplatin arm (9.6%) compared with other two arms (paclitaxel/cisplatin 2.8% vs. paclitaxel/carboplatin 5.8%). WHO grade above 2 non-hematologic GI toxicity occurred high in paclitaxel/carboplatin arm (5.2%) compared with other two arms(paclitaxel/cisplatin 3.4% vs. gemcitabine/cisplatin 2.5%). WHO grade above 2 non-hematologic excluding GI toxicity occurred high in paclitaxel/cisplatin arm(8.8%) compared with other two arms(paclitaxel/carboplatin 7.9% vs. gemcitabine/cisplatin 2.6%). Common side effects included nausea/vomiting, peripheral neuropathy and alopecia. Comparing toxicity profiles for the three regimens revealed no significant difference. Overall response rate was 22% for paclitaxel/cisplatin arm, 31% for paclitaxel/carboplatin arm, and 15% for gemcitabine/cisplatin arm. Comparing response rate for the three arms revealed no significant difference. The median survival period was 12.2 months for paclitaxel/cisplatin arm, 18.3 months for paclitaxel/carboplatin arm, and 8.3 months for gemcitabine/cisplatin arm. Comparing survival for the three arms revealed no significant difference. There were several limitations of this study, uncontrolled baseline disease, baseline toxicity, number of patient and number of effective cycles for the treatment group. Further well-designed study is required and pharmacist's role in ADR monitoring should be emphasized.
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Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture
Kim, Daesung,Yoo, Injae,Park, In-Cheol IEEE 2018 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.65 No.6
<P>An efficient decoding architecture for triple-error-correcting BCH codes is proposed by utilizing a lookup table (LUT) that stores the roots of the error locator polynomial instead of using the Chien search. Two roots of the polynomial equation are precomputed and stored in the LUT in order to relax the hardware complexity. To relax the complexity further, a new method to compress the LUT is additionally proposed. While a large portion of the LUT is filled with unnecessary information in the previous designs, this brief eliminates the redundant information by investigating an algebraic property of the equation. For BCH codes over GF(2<SUP>10</SUP>), the LUT size is reduced to 18% of the previous work. As a result, the proposed decoding architecture reduces the decoding latency by 38% and the equivalent gate count by up to 40% compared to the previous work, achieving a fast low-complexity triple-error-correcting BCH decoder.</P>
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Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns
Bongjin Kim,Injae Yoo,In-Cheol Park IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.3
<P>In this brief, we present how parallel-interleaved addresses generated by a quadratic permutation polynomial (QPP) interleaver are related to each other and propose a low-complexity parallel QPP interleaver based on the relationship. While a conventional parallel turbo decoder employs a number of interleavers as many as the parallel factor, the proposed method, which benefits from the arithmetic relationship denoted as the permutation pattern (PP), supports the parallel interleaving using only a single interleaver, resulting in a notable reduction of complexity. The strength of the proposed method stems from the fact that the PP is fully determined by only the decoding parameters, such as block size, parallel factor, and QPP coefficients. Experiment results on the Long Term Evolution turbo codes show that the proposed interleaver can significantly reduce the hardware complexity compared with conventional implementations.</P>
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