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Memristor Emulator for Memristor Circuit Applications
Hyongsuk Kim,Sah, M. Pd,Changju Yang,Seongik Cho,Chua, L. O. IEEE 2012 IEEE Transactions on Circuits and Systems I: Regul Vol.59 No.10
<P>A memristor emulator which imitates the behavior of a TiO<SUB>2</SUB> memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO<SUB>2</SUB> memristor model in real circuit.</P>
Memistor Is Not Memristor [Express Letters]
Hyongsuk Kim,Adhikari, S. P. IEEE 2012 IEEE circuits and systems magazine Vol.12 No.1
<P>This note clarifies the circuit-theoretic differences between a memristor and a memistor.</P>
Neural Synaptic Weighting With a Pulse-Based Memristor Circuit
Hyongsuk Kim,Sah, Maheshwar,Changju Yang,Roska, Tamá,s,Chua, Leon O. IEEE 2012 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.59 No.1
<P>A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models.</P>
김용진(Yongjin Kim),양창주(Changju Yang),김형석(Hyongsuk Kim) 대한전자공학회 2015 전자공학회논문지 Vol.52 No.8
본 연구에서는 TiO₂ 멤리스터와 동일한 동작특성을 갖는 멤리스터 에뮬레이터 회로를 비접지형 회로로 개발하였다. 대부분의 기존 멤리스터 에뮬레이터는 다른 멤리스터나 소자들과의 연결성을 고려하지 않은 접지 식으로 개발된 것들이다. 본 연구에서 개발한 멤리스터 에뮬레이터는 비접지식으로서, 출력 단을 접지할 필요가 없기 때문에 다른 소자들과 연결이 가능하여, 다양한 회로들과의 연결하여 동작을 확인하는데 사용할 수 있다. 개발한 멤리스터 에뮬레이터의 기능을 확인하기 위해서 저항과 직렬로 연결한 회로와 4개의 멤리스터 에뮬레이터를 직렬 및 병렬로 연결한 휘트스톤 브리지 회로를 구성하였다. 또한 이 브리지 회로가 신경망 시냅스의 가중치 연산이 가능함을 보였다. A floating type of memristor emulator which acts like the behavior of TiO₂memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.
아날로그 비터비 디코더에 있어서 기생 cap성분 최소화 layout 설계에 의한 신호전파 지연 개선
김인철(Incheol Kim),김현정(Hyunjung Kim),김형석(Hyongsuk Kim) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.4
A circuit design technique ttl reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is fur the PR(1.2,2.1) signal of DVD. The benefits arc low power consumption ami less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.