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Design of a High-Performance On-Chip Bus
Fred Adu Kumi,Seung-yong Park,Kwangki Ryoo 한국정보통신학회 2016 2016 INTERNATIONAL CONFERENCE Vol.8 No.1
In this paper, we propose a high-performance on-chip bus for system-on-chip design. The proposed bus is made up of two channels which allows simultaneously transactions to occur. Each channel has separate read and write buses and can also perform concurrent read and write transactions. The arbiter is designed to grant access based on the availability of the channel and the target slave. The proposed bus is designed at RTL with Verilog HDL using Xilinx ISE 14.7 and simulated with Modelsim and tested on HBE-SoC-IPD board equipped with Virtex-4 FPGA. Various tests are performed and the results are compared with AMBA AHB.