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- 저자 : 한석룡 (검색결과 9 건)
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Design of Hg₁_xCdxTe OMVPE System and ARIIV Reactor Chamber
한석룡(S. R. Hahn),J. D. Parsons 한국진공학회(ASCT) 1993 Applied Science and Convergence Technology Vol.2 No.4
Hg_(1-x)Cd_xTe 박막 성장을 위해 ARIIV(annular reactant inlet inverted vertical) reactor를 이용한 OMVPE(organometallic vapor phase epitaxy) 기구를 제작하였다. 본 논문에서는, 새로 고안한 ARIIV reactor 기술을 자세히 설명하였다. ARIIV reactor를 이용하면, 내부확산에 필요한 고온 처리 과정을 피할 수 있으며, Hg 혼합이 잘 된 균질한 Hg_(1-x)Cd_xTe 박막을 얻을 수 있다. The direct growth OMVPE system, designed specifically for direct growth of Hg_(1-x)Cd_xTe using annular rectant inlet inverted vertical (ARIIV) reactor, was constructed. This paper presents the detailed technical approach on a newly designed ARIIV reactor that increases Hg incorporation, imposes uniformity, and avoids the needs for high temperature processing to create alloys by interdiffusion approach.
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Cd₄SnSe6 및 Cd₄SnSe6 : Co²+ 單結晶의 光學的 特性
한석룡(Suk-Ryong Hahn),김화택(Wha-Tek Kim) 한국진공학회(ASCT) 1993 Applied Science and Convergence Technology Vol.2 No.4
화학수송법으로 Cd₄SnSe_6 및 Cd₄SnSe_6 : Co²+ 단결정을 성장시켰다. 성장된 단결정은 monoclinic structure를 갖고 있으며, 광학적 energy gap은 직접전이형으로 293K에서 Cd₄SnSe_6 단결정의 경우 1.68eV이고, Cd₄SnSe_6 : Co²+ 단결정의 경우 1.50eV 이다. Cd₄SnSe_6: Co²+ 단결정에서 cobalt 불순물에 의한 불순물 광흡수는 4879 ㎝^(-1), 5392 ㎝^(-1), 6247 ㎝^(-1)에서 나타났으며, 이들 peak는 Cd₄SnSe_6 단결정의 T_d symmetry site에 위치한 Co²+ ion의 energy 준위 사이의 전자전이에 의한 optical absorption이다. Cd₄SnSe_6 and Cd₄SnSe_6: Co²+ single crystals were grown by the chemical transport reaction (CTR) method. The grown single crystlas crystallize in the monoclinic structure and have the direct band gaps. The energy gaps of them are 1.68eV for Cd₄SnSe_6 and 1.50 eV for Cd₄SnSe_6 : Co²+ at 293K. The impurity optical absorption peaks due to cobalt doped with impurity appear at 4879 ㎝^(-1), 5392 ㎝(-1) and 6247 ㎝^(-1), and are attributed to the electron transitions between the split energy levels of Co²+ ion sited at T_d symmetry of Cd₄SnSe_6 single crystal.
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비냉각 적외선 열상장비용 CMOS Readout IC 설계
한석룡,윤동한,강대석,박재우,송성해,신경욱,우회구,윤태준,이상돈 金烏工科大學校 1998 論文集 Vol.19 No.-
A CMOS readout circuit for uncooled infrared Focal Plane Array (FPA) deteftor is presented, which is a key component in InfraRed (IR) imaging systems. The designed readout circuit satisfies various design requirements and constraints such as impedance matching, low noise, large dynamic range, low power dissipation and small pitch size. For impedance matching between the detector and preamplifier, a new circuit based on MOS diode structure with variable substrate biasing is devised. Also, tunable low pass filter with single-pole is used to suppress high frequency noise. In addition, a clamp circuit is used to enhance the signal-pole is used to suppress high frequency noise. In addition, a clamp circuit is used to enhance the signal-to-noise ratio of the readout output signals. A prototype 64×64 ROIC is designed using 0.65-㎛ 2P3M (double poly, tripple metal) N-Well CMOS process. It contains 62,000 devices including transistors, capacitors and resistors on an area of about 6.3×6.7㎟.
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HgCdTe를 이용한 Infrared Detector의 제조와 특성
김재묵,서상희,이희철,한석룡 한국군사과학기술학회 1998 한국군사과학기술학회지 Vol.1 No.1
HgCdTe Is the most versatile material for the developing infrared devices. Not like III-V compound semiconductors or silicon-based photo-detecting materials, HgCdTe has unique characteristics such as adjustable bandgap, very high electron mobility, and large difference between electron and hole mobilities. Many research groups have been interested in this material since early 70's, but mainly due to its thermodynamic difficulties for preparing materials, no single growth technique is appreciated as a standard growth technique in this research field. Solid state recrystallization(SSR), travelling heater method(THM), and Bridgman growth are major techniques used to grow bulk HgCdTe material. Materials with high quality and purity can be grown using these bulk growth techniques, however, due to the large separation between solidus and liquidus line on the phase diagram, it is very difficult to grow large materials with minimun defects. Various epitaxial growth techniques were adopted to get large area HgCdTe and among them liquid phase epitaxy(LPE), metal organic chemical vapor deposition(MOCVD), and molecular beam epitaxy(MBE) are most frequently used techniques. There are also various types of photo-detectors utilizing HgCdTe materials, and photovoltaic and photoconductive devices are most interested types of detectors up to these days. For the larger may detectors, photovoltaic devices have some advantages over power-requiring photoconductive devices. In this paper we reported the main results on the HgCdTe growing and characterization including LPE and MOCVD, device fabrication and its characteristics such as single element and linear array($8{\times}1$ PC, $128{\times}1$ PV and 4120{\times}1$ PC). Also we included the results of the dewar manufacturing, assembling, and optical and environmental test of the detectors.
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RF 마그네트론 스퍼터링 방법으로 제조한 (Ba,Sr)TiO$_3$ 박막의 유전 및 초전특성
박재석,김진섭,이정희,이용현,한석룡,이재신 한국세라믹학회 1999 한국세라믹학회지 Vol.36 No.4
RF 마그네트론 스퍼터링방법으로 Pt/Ti/NON/Si 기판 위에 $Ba_{0.66}$$Sr_{0.38}$$TiO_{3}$(BST) 박막을 증착한 다음 유전 및 초전특성을 살펴보았다. BST 박막을 증착할 때 기판온도를 300~-$600^{\circ}C$로 변화시킨 결과 기판온도가 증가할수록 박막의 결정성과 입도가 증가하여 유전율과 초전계수가 증가하였다. 한편 하부전극인 Pt의 증착조건이 BST 박막의 몰성에 미치는 영향도 살펴보았다. Pt의 증착온도와 Pt의 미세구조와 결정성뿐만 아니라 상부에 형성된 BST 박막의 배향성에도 큰 영향을 미쳤으며, 그 결과 BST의 초전특성에도 큰 영향을 미쳤다. BST 박막과 Pt 하부전극의 증착조건을 적정화함으로써 본 연구에엇는 상온에서 초전계수가 240 $nCcm^{-2}K^{-1}$인 BST 박막을 얻었다. The dielectric and pyroelectric properties of $Ba_{0.66}$$Sr_{0.38}$$TiO_{3}$(BST) thin films growtn on Pt/Ti/NON/Si us-ing RF magnetron sputtering have been investigated. With increasing the substrate temperature during de-position of the BST film in the range of 300-$600^{\circ}C$ the dielectric and pyroelectric constants of the film were increased due to improved crystallinity of the film. In addition the dependence of the microstructural and electrical properties of BST films onthe deposition temperature of the bottom Pt electrode was studied. The preferred orientation of the BST films as well as the microstructure of the Pt film was greatly in-fluenced by the deposition temperature of the bottom Pt electrode was studied. The preferred orientation of the BSt films as well as the microstructure of the Pt film was greatly in-fluenced by the deposition temperature of the bottom Pt electrodes. and thus so were the pyrolelectric pro-perties of the BST film. The highest value of pyroelectric coefficient at room temperature obtained in this work was $nCcm^{-2}K^{-1}$ which is much higher than those previously reported on other perovskite fer-roelectric thin films.
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비냉각 열상장비용 $64\times64$ IRFPA CMOS Readout IC
우회구,신경욱,송성해,박재우,윤동한,이상돈,윤태준,강대석,한석룡 대한전자공학회 1999 電子工學會論文誌, C Vol.c36 No.5
비냉각 열상장비의 핵심 부품으로 사용되는 InfraRed Focal Plane Array(IRFPA)용 CMOS ReadOut IC (ROIC)를 설계하였다. 설계된 ROIC는 64×64 배열의 Barium Strontium Titanate(BST) 적외선 검출기에서 검출되는 신호를 받아 이를 적절히 증폭하고 잡음제거 필터링을 거쳐 pixel 단위로 순차적으로 출력하는 기능을 수행하며, 검출기 소자와의 임피던스 매칭, 저잡음 및 저전력 소모, 검출기 소자의 pitch 등의 사양을 만족하도록 설계되었다. 검출기 소자와 전치 증폭기 사이의 임피던스 매칭을 위해 MOS 다이오드 구조를 기본으로 하는 새로운 회로를 고안하여 적용함으로써 표준 CMOS 공정으로 구현이 가능하도록 하였다. 또한, tunable 저역통과 필터를 채용하여 신호대역 이상의 고주파 잡음이 제거되도록 하였으며, 단위 셀 내부에 클램프 회로를 삽입하여 출력신호의 신호 대 잡음비가 개선되도록 하였다. 64×64 IREPA ROIC는 0.65-㎛ 2P3M (double poly, tripple metal) N-Well CMOS 공정으로 설계되었으며, 트랜지스터, 커패시터 및 저항을 포함하여 약 62,000여개의 소자로 구성되는 코어 부분의 면적은 약 6.3-{{{{ { mm}_{ } }}}}×6.7-{{{{ { mm}_{ } }}}}이다. A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.
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