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개선된 MRME 알고리즘을 이용한 H.264 움직임 추정기 설계 및 FPGA 검증
진군선,강진아,임재윤 제주대학교 공과대학 첨단기술연구소 2004 尖端技術硏究所論文集 Vol.15 No.2
This paper presents an architectural enhancement to reduce the data load of the Multi-Resolution motion estimation. Our approch is based on eliminating unnecessary data load using memory reuse. New hardware architecture for integer-pel ME(motion estimation) dedicated to H.264/AVC is proposed. The proposed architecture supports all 7 modes (16x16, 16x8, 8x16, 8x8, 8x4, 4x8, and 4x4) for variable block size ME. The features of our design are 2-D PE(processing element) array and SAD merging scheme. A pipelined and shared datapath architecture for motion estimation unit are designed to improve the system performance at the reduced hardware complexity.