RF 송수신 회로의 적층형 PAA 패키지 모듈

지용,남상우,홍석용,Jee, Yong,Nam, Sang-Woo,Hong, Seok-Yong 대한전자공학회 2001 電子工學會論文誌-SD (Semiconductor and devices) Vol.38 No.10

본 논문에서는 RF(Radio Frequency) 회로의 구현 방법으로서 3차원 적층형태의 PAA(Pad Area Array) 패키지 구조를 제시하였다. 지능 교통망 시스템(Intelligence Traffic System)을 위한 224㎒의 RF 시스템을 적층형 PAA 패키지 구조에 적용시켜 구현하였다. 적층형 PAA 패키지 구성 과정에서는 RF 회로를 기능별, 주파수별로 분할하였고 3차원적인 적층형태의 PAA 구조로 설계한 후 분할된 단위 모듈의 RF 동작특성과 3차원 적층형 PAA 패키지 모듈의 전기적 특성을 개별적으로 분석하였다. 적층형 PAA RF 패키지가 갖는 연결단자인 공납(Solder Ball)에 대한 전기적 파라미터 측정결과 그 전기적 특성인 기생 캐패시턴스와 기생 인덕턴스는 각각 30fF, 120pH로 매우 미세하여 PAA 패키지 구조인 RF 시스템에 끼치는 영향이 무시될 수 있음을 확인하였고, 구성된 송수신단은 HP 4396B network/spectrum analyser로 측정한 결과 224㎒에서 수신단, 송신단 증폭이득은 각각 22dB 27dB. 나타나서 설계값에 비하여 3dB감소 된 것을 알 수 있었다. 이는 설계와 제작과정 사이의 차이로 판명되었으며 수동부품 보정방법을 통하여 각 단위모듈의 입출력 임피던스 정합을 이루어 각각 24dB, 29dB로 개선시킬 수 있었다. 따라서, 본 실험에서는 RF 회로를 기능별로 모듈화하고 3차원 적층형 PAA 패키지 구조로 구현하여 전기적 특성을 개선시킬 수 있음을 확인하였다. This paper presents a three dimensional stacked pad area away (PAA) package configuration as an implementation method of radio frequency (RF) circuits. 224MHz RF circuits of intelligence traffic system(ITS) were constructed with the stacked PAA RF pakage configuration. In the process of manufacturing the stacked PAA RF pakage, RF circuits were partitioned to subareas following their function and operating frequency. Each area of circuits separated to each subunits. The operating characteristics of RF PAA package module and the electrical properties of each subunits were examined. The measurement of electrical parameters for solder balls which were interconnects for stacked PAA RF packages showed that the parasitic capacitance and inductance were 30fF and 120pH, respectively, which might be negligible in PAA RF packaging system. HP 4396B network/spectrum analyzer revealed that the amplification gain of a receiver and transmitter at 224 MHz was 22dB and 27dB, respectively. The gain was 3dB lower than designed values. The difference was probably generated from fabrication process of the circuits by employing commercial standard

PAA(Pad Area Array)을 이용한 ITS RF 모듈의 3차원적 패키지 구현

지용,박성주,김동영,Jee, Yong,Park, Sung-Joo,Kim, Dong-Yong 대한전자공학회 2001 電子工學會論文誌-SD (Semiconductor and devices) Vol.38 No.1

본 논문에서는 RF 회로의 3차원 적층 구조를 설계하고 RF 회로의 특성개선 효과를 살펴보았다. 3차원적 RF 회로를 구현하기 위하여 분할 설계 기준을 제안하였으며 이에 따라 RF 회로를 기능별, 동작 주파수별로 분할하여 구현하였다. 분할된 하위 모듈을 3차원으로 적층 연결할 수 있도록 PAA 입출력 단자구조를 이용하여 3차원 형태의 ITS RF 시스템을 제작하였다. 이에 따라 아날로그 신호와 디지털 신호, DC 전원이 혼재되어 있는 ITS(지능형 교통관제 시스템) 224MHz RF 모듈을 구성되는 회로를 특성 임피던스 정합과 시스템의 동작 안정도를 고려하여, 기능별로는 송신부, 수신부, PLL(Phase Locked Loop)부, 전원부로 분할하였고 주파수별로는 224MHz, 21.4MHz, 및 450kHz~DC의 주파수 대역으로 분할하여 설계하였다. RF 회로 모듈을 구현하는 과정에서 224MHz 대역에서 동작하는 송신부와 수신부 증폭회로는 설계치와 일치하는 18.9㏈, 23.9㏈의 이득, PLL부와 전원부는 위상 고정, 정전원 입력의 동작특성을 최대화시킬 수 있었다. 3차원 구조의 RF 모듈은 2차원의 평면구조의 단일 기판 구성방법과 비교하여 부피 및 배선길이에서 각각 76.9%, 28.4%를 감소시킨 $48cm^3$, 1.8cm를 나타내었고, 열적 성분인 최고 동작 온도특성은 37% 감소한 $41.8^{\circ}C$를 나타났다. PAA형 3차원 적층 구조는 고속 고밀도 저전력의 특성을 가지며, 저비용으로 구현할 수 있으며 RF 주파수 영역에서 각 모듈을 기능별, 주파수별로 모듈화해 제품의 기능을 가변적으로 변화시켜줄 수 있음을 알 수 있었고, RAA 형태의 입출력 단자로 연결함으로써 단일 양면 기판으로 구현되던 2차원적 RF 회로 모듈의 부피와 전기적 동작 특성과 열적 특성을 개선시킬 수 있었다. This paper presents three dimensional structure of RF packages and the improvement effect of its electrical characteristics when implementing RF transceivers. We divided RF modules into several subunits following each subunit function based on the partitioning algorithm which suggests a method of three dimension stacking interconnection, PAA(pad area array) interconnection and stacking of three dimensional RF package structures. 224MHz ITS(Intelligent Transportation System) RF module subdivided into subunits of functional blocks of a receiver(RX), a transmitter(TX), a phase locked loop(PLL) and power(PWR) unit, simultaneously meeting the requirements of impedance characteristic and system stability. Each sub­functional unit has its own frequency region of 224MHz, 21.4MHz, and 450KHz~DC. The signal gain of receiver and transmitter unit showed 18.9㏈, 23.9㏈. PLL and PWR modules also provided stable phase locking, constant voltages which agree with design specifications and maximize their characteristics. The RF module of three dimension stacking structure showed $48cm^3$, 76.9% reduction in volume and 4.8cm, 28.4% in net length, 41.8$^{\circ}C$, 37% in maximum operating temperature, respectively. We have found that three dimensional PAA package structure is able to produce high speed, high density, low power characteristics and to improve its functional characteristics by subdividing RF modules according to the subunit function and the operating frequency, and the features of physical volume, electrical characteristics, and thermal conditions compared to two dimensional RF circuit modules.

DRAM 메모리 모듈 제작에서 MCM-L 구조에 의한 설계

지용,박태병,Jee, Yong,Park, Tae-Byung 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.5

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.

TDX-10 가입자 정합회로의 Digital, Analog 성능 측정

이용운(Yong-Woon Lee),정준건(Jun-Gun Chung),장승혁(Seung-Hyeock Chang),지용(Yong Jee),남홍순(Hong-Soon Nam),김진태(Jin-Tae Kim),이현(Hun Lee) 한국통신학회 1994 한국통신학회 학술대회논문집 Vol.1994 No.7

128K$\times$8bit SRAM 메모리 다중칩 패키지 제작

김창연,지용,Kim, Chang-Yeon,Jee, Yong 대한전자공학회 1994 전자공학회논문지-A Vol.31 No.3

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

다층 기판 위에 표면실장된 SRAM 모듈 설계 제작

김창연,지용,Kim, Chang-Yeon,Jee, Yong 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.3

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

TFT/LCD 시스템 패키지 전기적 특성 분석 및 설계도구의 구현

임호남,지용,Yim, Ho-Nam,Jee, Yong 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.12

This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

광소자 package 기술

유병권,지용,Yoo, Byeong-Gwon,Jee, Yong 대한전자공학회 1994 전자공학회지 Vol.21 No.2

CPW 급전 광대역 사각 슬롯 안테나 설계

최순신,김준일,지용,Choi, Soon-Shin,Kim, Joon-Il,Jee, Yong 대한전자공학회 2005 電子工學會論文誌-TC (Telecommunications) Vol.42 No.11

본 논문에서는 광대역에서 동작하는 대역폭 조절 패치를 갖는 CPW 급전 사각 슬롯 안테나를 제시하였다. 안테나 설계 방법으로서 구조적 변수인 사각 슬롯의 가로폭 및 세로폭을 이용하여 반파장 다이폴 안테나 특성을 보이는 낮은 공진 주파수와 높은 공진 주파수 영역을 설정하였고, 대역폭 조절 패치를 이용한 $50{\Omega}$ 임피던스 정합 조절 과정을 통하여 $20GHz\~33GHz$ 영역에서 동작하는 $50\%$ VSWR=2 임피던스 대역폭을 지닌 안테나 구조를 제시하였다. 안테나 사각 슬롯의 가로폭을 4.6mm로, 세로폭을 3.5mm로, 비율이 $70\%$정도인 안테나 구조에서 중간 주파수 26GHz, 대역폭 $20GHz\~33GHz$의 측정 결과를 나타냈다. 이 결과는 의료용 안테나가 대역폭 조절 패치를 이용할 때 단순한 사각 슬롯 안테나의 구조로 구현됨을 보여 주었다 This paper presents the structure of a broadband coplanar waveguide(CPW) fed square slot antenna with a impedance bandwidth tuning patch. The designing method of the antenna suggests that two resonant frequencies are excited as a dual-frequency dipole antenna following the dimensions of the square slot. In other words, the lower resonant frequency mainly depends on the slot width and the higher one its length. A CPW fed square slot antenna with a impedance tuning patch was measured to $20GHz^\~33GHz$, $50\%$, VSWR=2 impedance bandwidth by adjusting the dimensions of the tuning patch when the slot length had $70\%$ of its width. This result shows that a medical CPW fed antenna is easily implemented with a simple square slot structure including a bandwidth tuning patch in the center.

2차원 이산 웨이브렛 변환을 위한 효율적인 VLSI 구조

반성범,박래홍,지용,Pan, Sung-Bum,Park, Rae-Hong,Jee, Yong 대한전자공학회 2000 電子工學會論文誌-SP (Signal processing) Vol.37 No.1

This paper proposes efficient VLSI architectures for computation of the 2- D discrete wavelet transform (DWT). The two proposed VLSI architectures for the 2- D DWT are constructed based on block-based computation Each $M{\times}N$ ($N{\times}M$) block DWT is performed along the row (column) direction simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively The proposed architectures compute the lowpass and highpass output sequences of the 1 - DWT along the row and column directions using a single architecture In alternate clock cycles Therefore the extra processing units required for the proposed architectures are much smaller than those of the conventional architectures They are modeled In very high speed Integrated circuit hardware description language (HIDL) and Simulated to show their functional validity. 본 논문은 2차원 DWT 계산을 위한 효율적인 VLSI 구조를 제안한다 제안한 두 개의 구조는 $M{\times}N$ ($N{\times}M$) 블록 단위로 2 D DWT를 계산한다 각각의 블록에서 2 D DWT의 계산은 행 (열) 방향으로 동시에 계산한다 M은 필터 탭 수를 나타내고 N은 열 (행)을 나타낸다 그리고 행과 열 방향으로 1차원 DWT를 계산할 때 저주파와 고주파 성분을 하나의 구조에서 번갈아 계산하도록 하였다 그러므로 제안한 구조는 기존의 구조에 비해 부가적인 처리 유닛이 적게 필요하다 VHDL를 이용하여 모델링하고 시뮬레이션하여 제안한 구조가 정상적으로 동작함을 확인하였다.