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- 저자 : 손윤구(Yoon Koo Sohn) (검색결과 7 건)
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김민주(Min-Joo Kim),손윤구(Yoon-Koo Sohn) 한국정보과학회 1992 정보과학회논문지 Vol.19 No.5
중앙 집중식 데이타베이스 시스템에 적용되는 질의 평가식은 CPU 사용과 디스크 접근 횟수 평가를 근간으로 하고 있다. 디스크 접근 횟수는 질의 처리 중에 생성되는 중간결과에 따라 달라지며 중간결과는 프레디키트와 실제의 데이타에 따라 달라지므로 디스크 접근 횟수를 정확하게 평가한다는 것은 어려운 일이다. 본 논문에서는 디스크 접근 횟수를 합리적으로 평가하기 위하여 인덱스된 애트리뷰트의 역할에 따라 질의 처리형태를 분류하고 그에 따른 평가식을 제안하였다. 제안된 평가식의 타당성을 실험으로 확인하였으며 최적화 비용을 줄이기 위한 경험적 규칙도 제시하였다. The cost formula used for most centralized database systems is based on the estimation of CPU use and the number of disk accesses. The disk access number depends on the intermediate results of the query and these results depend on the predicate and the actual data;thus, accurate calculating the disk access number is a difficult problem. In this paper, to estimate these numbers more reasonably, the various query processes are classified by the role of an indexed attribute and the estimation formula for these classes are proposed. The validation of the proposed formula is verified by the experiment. In addition, the heuristic rules for decreasing the cost of optimization are proposed.
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윤영우(Young Woo Yoon),손윤구(Yoon Koo Sohn) 한국정보과학회 1992 정보과학회논문지 Vol.19 No.6
Tree 중계방식을 개선하여, 요청신호와 승인신호로써 lookahead 정보를 생성하고 이것을 이용하여 각 중재모듈들이 동시에 중재함으로써 중재시간이 O(1) 즉, 프로세서의 개수에 관계없이 일정하며, 현재의 승인에 관계된 중재모듈들은 다음 중재에서는 우선순위를 바꿈으로써 프로세서간에 공정한 기회가 주어지는 비동기식 하드웨어 중재기를 개발한다. A modified asynchronous tree arbiter is developed. In the arbiter, every arbiter module arbitrates simultaneously using the lookahead information extracted from the request signals and grant signals. As the result, the order of arbitration time is O(1), that is, independent of the number of processors. And for the purpose of fairness, the priorties of the arbiter modules concerned with current grant are changed in the next arbitration.
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孫潤求 영남대학교 공업기술연구소 1985 연구보고 Vol.13 No.2
As the (7,3) cyclic code is applied to the design of the counter, unit block is a three-bit count module with four redundant bits. Thus the proposed implementation is an approach for realizing the modular LSI of sequential circuit with high information rate. More than three-bit circuit realization is attainable by connecting three-bit count modules in cascade. In this paper, a synthesis procedure for realizing a single-failure-tolerant parallel binary counter with double-failure-detecting scheme is presented. Using the orthogonizable (7,3) cyclic code, double-failure-detecting count logic is accomplished in addition to single-failure-tolerant count logic. The proposed techniques can be applied in principle to other sequential circuits to increase its reliability.
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Mini-Floppy Disk Drive 의 Handler 에 관한 硏究
李在己,孫潤求 嶺南大學校 工業技術硏究所 1982 연구보고 Vol.10 No.2
With the increasing popularity of microcomputer system, mini-floppy disk drive has been widely used for the input/output storge of the host system becaues of its high speed and a large capacity to the cost. In this paper, floppy disk drive (FDD) has been presented as I/O data storage which user can easily handle the desired data by merely pressing a function key. For this purpose, the author has developed a handler to meet the requirements of FDD such as timing delay. And also, variable block size and soft sectoring are controlled by this handler. Implementing the developed handler, the author has obtained satisfactory result.
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孫潤求 嶺南大學校 工業技術硏究所 1977 연구보고 Vol.5 No.1
Memories are one modular of Computer systems that are largely iterative. Specifically in the case of real-time operation, it is difficult to replace bad elements with good one. Under such conditions, the use of error correcting code may be desirable. Therefor, in this paper, (7,3) cyclic code is used. The problem of making a memory of W words, each 16 bit long, using semiconductor LSI. One reasonable partitioning is to build the equivalent of a core memory bit plane, complete with all associated circuitry, including address decoding, on one wafer. An 8-bit memory unit is a common subunit for modern computers. A parity check bit is added on a 1 Byte. The 9 bits(8 bit+1 parity check bit)are broken into subgroups of 3, then 7 bit (3 data bit+4 redundant bits) of storage can be used in a single error correcting double error detecting arrangement to store 3 data bits. Consequently a single error correction in a section is equivalent of multiple error correction in a word. In the case of error detection is also same as above mentioned
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Seqence Generator의 신뢰성 향상을 위한 冗長技術 利用
孫潤求 嶺南大學校 工業技術硏究所 1980 연구보고 Vol.8 No.1
Recently the facts are recognized that even the α-ray or can cause the failure on VLSI chip, So the sequential circuits must have certain redundant circuits in order to be capable of correcting error. For this reason (7.3) Cyclic code is taken into consideration. In this paper a synthesis procedure for realizing a single failure-tolerant sequence generator with double-error self-detecting scheme using orthogonizable (7.3) cyclic code are presented.
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손윤구,이규호 嶺南大學校 工業技術硏究所 1986 연구보고 Vol.14 No.1
In this paper, STA(structured assembler) is suggested and a preprocessor for it has developed. The designed statements follow LL(1) grammer for simple parsing. The preprocessor accepts CP/M's M80 macroassembler source codes containing the designed block-structured statements and then outputs pure assembler codes. From a number of testing, it's documentability as good as most high-level programming languages and the efficiency of codes resulting from optimization routine have certified.
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