http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : 마헤스워 사 (검색결과 5 건)
- 무료
- 기관 내 무료
- 유료
-
마헤스워 사,양창주,김성우,김형석 제어로봇시스템학회 2009 제어로봇시스템학회 합동학술대회 논문집 Vol.2009 No.12
The Decoding performance of analog differential Viterbi decoder and analog feed forward differential Viterbi decoder has been investigated. In Viterbi decoder, the optimal path from the specific starting state of the decoding stage to a state of output stage needs to be computed. The starting state in analog differential viterbi decoder is varied depending on previous decoding information at the output stage, the structure requires more complicated circuits in determination and designation of starting state. The feed forward differential architecture comes from the idea that decoding is mainly done through first state to several stages by allowing the optimum path from multiple nodes of trellis diagram. The optimal path computed from multiple starting states on the decoding stage to a state on the output stage is simpler in hardware. We found that the performance of the circuits with the feed forward differential architecture is similar to that with the analog differential structure when the constraint (size) of the Viterbi decoder is small. In this paper, the size at which the decoder can still be used is investigated through simulations.
-
A Feed forward Differential Architecture for the Analog PRML Viterbi Decoder
Maheshwar Pd. Sah(마헤스워 사),Changju Yang(양창주),Hyongsuk Kim(김형석) 제어로봇시스템학회 2010 제어로봇시스템학회 합동학술대회 논문집 Vol.2010 No.12
In this paper, an analog parallel processing circuit in the form of feed forward differential architecture is proposed to implement on analog PRML Viterbi decoder. It is based on the idea that the decoding of PRML is done mainly with the information of the first several number of stages. Several benefits including higher speed, no path memory, no trace back unit and no A/D converter are required for the decoding of the signals. Most of the conventional analog parallel processing-based PRML decoders are differential architecture with the feedback, where states are changed depending on the previous decoded data. The architecture used in this paper is without feedback, where error metric accumulation is allowed to start from odd and even input of subtrellis. It is simpler than that of the conventional analog parallel processing structure with similar decoding performance. The feature of proposed architecture is investigated through simulation results.
-
Memristor Circuit for Artificial Synaptic Multiplication
Maheshwar Pd. Sah(마헤스워 사),Changju Yang(양창주),이청호,Hyongsuk Kim(김형석) 제어로봇시스템학회 2011 제어로봇시스템학회 각 지부별 자료집 Vol.2011 No.7
A memristor circuit is proposed to synaptic multiplication of artificial neural networks by using ohms law v = M(q) x i. The weight and synaptic processing can be performed positively or negatively through a share input terminal. Several benefits like compact integration, lower power consumption and analog processing is applicable in the circuit. The simulations of the proposed circuit are analyzed with Hewlett-Packard (HP) TiO₂ memristor model.
-
아날로그 PRML 디코딩 회로 구현 시의 미스 매칭 문제 완화를 위한 입력 심볼 에러 값 증폭
양창주(Changju Yang),마헤스워 사(Maheswar Sah),김형석(Hyongsuk Kim) 大韓電子工學會 2009 電子工學會論文誌-SD (Semiconductor and devices) Vol.46 No.8
차동형 아날로그 PRML 디코더의 하드웨어 구현 시에 발생하는 mismatching 문제를 해결하기 위해서 입력 심볼 에러를 증폭함으로써 에러 정정 효과를 향상시키는 방법을 제안하였다. 차동형 아날로그 PRML 비터비 디코더는 축약된 길이만큼의 트렐리스 다이아그램 회로를 2 개 구성하고, 그 중 한 회로는 0에 해당하는 가지들을 절단하고, 다른 회로는 1에 해당하는 가지들을 절단하여 두 회로의 출력을 비교함으로써 디코딩한다. 이 때, 두 회로 출력 값의 차이가 작을 경우에는 하드웨어 구현시의 mismatching 때문에 디코딩 에러가 발생할 수 있다. 본 논문에서는 입력 심볼 에러 값들을 증폭함으로서 큰 경로 에러값들은 saturation시키는 대신, 작은 경로 에러 값들 간에는 구별 성을 키움으로써 결과적으로 0 혹은 1 간의 구별 마진이 커지게 하는 방법을 제안하였다. 회로의 디코딩 성능 개선효과를 보이기 위해 시뮬레이션 결과를 제시하였다. An idea to improve the performance of error correction with the amplification of input symbol errors is proposed to ease the mismatching problem which occurs in the hardware implementation of the differential analog PRML decoder. The differential analog PRML decoder is the decoder with two blocks of trellis diagram one of which is without branches of “0” and the other one is without the branches of “1”. Decoding is performed by comparing the outputs of two blocks. The decoding error is likely to occur when the difference of two outputs is very small and the hardware implementation is not precise due to mismatching. The proposed idea is to increase the discrimination margin for the output “0” and “1” by amplifying the symbol error while the larger path metrics are saturated. To show the performance improvement of decoding with the proposed idea, simulation results are included.
-
Analysis of Electrical Features of Serially and Parallelly connected Memristor Circuits
람 카지 부다토키,마헤스워 사,김주홍,김형석,Budhathoki, Ram Kaji,Sah, Maheshwar Pd.,Kim, Ju-Hong,Kim, Hyong-Suk The Institute of Electronics and Information Engin 2012 電子工學會論文誌-CI (Computer and Information) Vol.49 No.5
저항, 콘덴서, 및 인턱터와 함께 4의 회로 소자로 알려진 멤리스터가 개발되었으나, 아직 그 전기적 특성이 충분히 해석되지 않고 있다. 멤리스터들은 연결된 극성에 따라서 저항이 증가 혹은 감소하며, 직렬 혹은 병렬연결 형태에 따라서 그 동작 특성이 다양해진다. 본 연구에서는 HP의 $TiO_2$ 멤리스터를 모델로 하여 다양한 직 병렬회로에 대한 전기적 특성을 분석하였다. 이를 위해서 사인파 입력신호에 대해서 나타나는 전압-전류 간의 히스테르시스 루프의 다양한 모양을 분석하였다. 본 멤리스터 연구결과는 멤리스터 소자에 대한 특성 이해와 논리 회로 및 뉴런 셀에의 응용회로들의 특성을 분석하는데 유용하게 사용될 수 있다. Memristor which is known as fourth basic circuit element has been developed recently but its electrical characteristics are not still fully understood. Memristor has the incremental and decremental feature of the resistance depending upon the connected polarities. Also, its operational behavior become diverse depending on its connection topologies. In this work, electrical characteristics of diverse types of serial and parallel connections are investigated using the HP $TiO_2$ model. The characteristics are analyzed with pinched hystersis loops on the V-I plane when sine input signal is applied. The results of the work would be utilized usefully for analyzing the characteristics of memristor element and applications to logic circuit and neuron cells.
ScienceON연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
