차량 추돌 방지 레이더용 24-GHz 전력 증폭기 설계

노석호,류지열,Noh, Seok-Ho,Ryu, Jee-Youl 한국정보통신학회 2016 한국정보통신학회논문지 Vol.20 No.1

본 논문에서는 차량 추돌 방지 단거리 레이더용 24-GHz CMOS 고주파 전력 증폭기 (RF power amplifier)를 제안한다. 이러한 회로는 클래스-A 모드 증폭기로서 단간 (inter-stages) 공액 정합 (conjugate matching) 회로를 가진 공통-소스 단으로 구성되어 있다. 제안한 회로는 TSMC $0.13-{\mu}m$ 혼성신호/고주파 CMOS 공정 ($f_T/f_{MAX}=120/140GHz$)으로 설계하였다. 2볼트 전원전압에서 동작하며, 저전압 전원에서도 높은 전력 이득, 낮은 삽입 손실 및 낮은 음지수를 가지도록 설계되어 있다. 전체 칩 면적을 줄이기 위해 넓은 면적을 차지하는 실제 인덕터 대신 전송선(transmission line)을 이용하였다. 설계한 CMOS 고주파 전력 증폭기는 최근 발표된 연구결과에 비해 $0.1mm^2$의 가장 작은 칩 크기, 40mW의 가장 적은 소비전력, 26.5dB의 가장 높은 전력이득, 19.2dBm의 가장 높은 포화 출력 전력 및 17.2%의 가장 높은 최대 전력부가 효율 특성을 보였다. In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

Design of Low-Power 24-GHz CMOS Mixer

Seok-Ho Noh(노석호),Jee-Youl Ryu(류지열) 제어로봇시스템학회 2021 제어·로봇·시스템학회 논문지 Vol.27 No.12

This paper proposes a low-power 24-GHz CMOS down-conversion mixer for the automotive radar. This circuit operates at the operation frequency of 24 GHz, and it contains low-power circuit technique. The proposed circuit is also fabricated using 65-nm RF CMOS(radio frequeny complementary metal-oxide-semiconductor) process. The circuit is powered using a 1.2-V supply with the bias voltage of 0.8 V for the low-power technique. This circuit also has fully-differential scheme to reduce RF noise, and harmonic distortions. The proposed mixer showed lower power dissipation of 6.5 mW with a high conversion gain and very small chip area of 0.01 mm2 as compared to conventional research results.

㎓-대역 저잡음 증폭기의 선형성 향상에 관한 연구

노석호(Seok-Ho Noh),류지열(Jee-Youl Ryu) 한국정보기술학회 2019 한국정보기술학회논문지 Vol.17 No.9

This paper presents study results for linearity improvement of ㎓-band low noise amplifier(LNA). To verify this linearity improvement, we fabricated the proposed circuit using TSMC 0.13-㎛ mixed signal/RF BiCMOS SiGe process(f<SUB>T</SUB>/f<SUB>MAX</SUB>=120/140㎓). The fabricated amplifier also operates at the power supply of 1.2V, and it is implemented to operate at the frequency of 2.4㎓. We used the MOS-BJT derivative superposition(MBDS) technique to achieve high linearity. To reduce the second-order nonlinear transconductance coefficient related to the enhancement of linearity, the LC tank circuit is paralleled in the emitter of bipolar transistor. We also connected two fee㏈ack capacitances in the base-to-collector and gate-to-drain capacitances to adjust the phase of third-order nonlinear coefficients of bipolar and MOS transistors, respectively. The proposed LNA showed excellent IIP3 of 26.7㏈m compared to recently published results.

저전력 24㎓ 저잡음 증폭기 개발

노석호(Seok-Ho Noh),류지열(Jee-Youl Ryu) 한국정보기술학회 2020 한국정보기술학회논문지 Vol.18 No.8

This paper presents low-power 24-㎓ CMOS low noise amplifier(LNA). This circuit is implemented using 65-㎚ RF CMOS process(f<SUB>T</SUB>/f<SUB>MAX</SUB>=70/90㎓). The low noise amplifier is powered by 1.2V supply, and it is designed to operate at the operation frequency of 24㎓. The proposed LNA has cascode scheme to decrease power consumption and to increase voltage gain, and it is optimized to minimize noise figure. This circuit is applicable to 5th generation(5G) mobile communication network and automotive collision avoidance radar system. The proposed circuit showed the lowest power consumption of 4.2㎽ and the smallest die area of 0.5×0.5㎟. This circuit also showed high voltage gain of approximately 31㏈, low noise figure of 2.71㏈, but it need to improve linearity for IIP3 of 2.8㏈m as compared to conventional research results.

프린터의 재활용 토너용 주변 회로의 ASIC 개발

노석호(Seok-Ho Noh),신건순(Gun-Soon Shin) 한국정보기술학회 2007 한국정보기술학회논문지 Vol.5 No.3

According as production of revival toner becomes difficult gradually by chip by toner residual quantity detection inning conglutinated to printer to meaning that do customer service managing information of toner cartridge that universal laser printer makers use in printer, discrepancy is worried in revival toner production. Therefore, research that see wishes to develop toner residual quantity detection circuit conglutinated compulsorily to produce revival toner to semi-conductor chip. Bulk of toner residual quantity detection return trip conglutinated in toner of operational printer current is comparative big state by using PCB substrate, therefore is incongruent to use in light weight print miniaturized more. This development does return trip miniaturized such as this to develop competitive product by doing one chip.

차량 추돌 예방 레이더를 위한 24GHz CMOS 믹서 설계

노석호(Seok-Ho Noh),류지열(Jee-Youl Ryu) 한국정보기술학회 2014 한국정보기술학회논문지 Vol.12 No.11

In this paper, we propose 24GHz CMOS mixer for automotive collision avoidance radar. This circuit operates at the operation frequency of 24GHz, and it contains Gilbert cell type. The proposed circuit is also designed using TSMC 0.13μm mixed signal/RF CMOS process (f<SUB>T</SUB>/f<SUB>MAX</SUB>=120/140GHz). The circuit operates at the supply voltage of 2V, and it is designed to have high conversion gain, low conversion loss and low noise figure in the low supply voltage. To make excellent isolation characteristics between LO and RF, we designed double-balanced topology. The mixer used transmission lines instead of the real inductor to reduce total chip area and to get accurate line phase shift. The proposed circuit showed the highest conversion gain of 10.96dB, IIP3 of 7.6dBm and FoM (figure of merit) of 14.4dB, and the smallest power consumption of 5mW and chip size of 0.2×0.2m² as compared to recently reported research results. It also showed excellent noise figure of 12.9dB, input return loss (S11) of -43.64dB, and LO-RF isolation (S12) of -49.3dB as conventional research results, respectively.

아날로그 집적회로 결함 검출을 위한 새로운 검사방식

노석호(Seok-Ho Noh),류지열(Jee-Youl Ryu) 한국정보기술학회 2014 한국정보기술학회논문지 Vol.12 No.12

This paper presents a new test technique for fault detection of analog integrated circuits. This test technique can detect various faults such as open, short, near open and near short from the fabrication step of analog integrated circuits. It is also capable of diagnosing specific faults from transistors, resistors, inductors, capacitors in integrated circuits, etc.. This technique discriminates defective or defect-free cases by measuring transient step current of power supply and output response, respectively. To verify performance of the proposed test technique, we designed wideband CMOS operational amplifier as a typical analog integrated circuits. It is designed using TSMC 0.18μm CMOS technology. The proposed technique showed an excellent fault detection capability of more than 99% from total 80 samples for various faults such as open, short, near open and near short. This test technique is inexpensive and simple.

차량 충돌 방지 근거리 레이더용 24GHz 저 잡음 증폭기 설계

노석호(Seok-Ho Noh),류지열(Jee-Youl Ryu) 한국정보기술학회 2013 한국정보기술학회논문지 Vol.11 No.10

In this paper, we propose ultra small 24GHz low noise amplifier (LNA) for side- and rear-looking automotive collision avoidance based on short range radar (SRR). The proposed circuit has a 2-stage cascode structure to improve voltage gain of the amplifier, and it uses transmission lines instead of inductors to reduce the total chip size. We designed this circuit using TSMC 0.13μm mixed signal/RF CMOS process (f<SUB>T</SUB>/f<SUB>MAX</SUB> =120/140GHz). We used the radio frequency layout techniques to reduce side effects from the parasitic capacitances related to deterioration in the circuit performance at the radio frequency band of 24GHz. The proposed circuit in this paper showed the smallest chip size of 0.2×0.2㎟, the highest voltage gain of approximately 42dB, the lowest noise figure of approximately 3.5dB, and the most excellent IIP3 of 2.8dBm as compared to recently reported research results.

차량 레이더용 77GHz 전력 증폭기 구현

노석호(Seok-Ho Noh),류지열(Jee-Youl Ryu) 한국정보기술학회 2018 한국정보기술학회논문지 Vol.16 No.9

This paper presents a low-power high-gain 77GHz power amplifier for automotive collision avoidance radar. The proposed circuit consists of a conjugate matching circuit stage to match input and inter-stage, and 2-stage cascode amplification stage to increase power gain. This circuit is designed using 0.18μm Bipolar/CMOS/DMOS (BCD) 1-poly 4-metal process (f<SUB>T</SUB>/f<SUB>MAX</SUB> =100/130GHz) with the top metal thickness layer of 3μm. This amplifier is realized to have low noise figure, low power consumption, and high power gain at a supply voltage of 2V. We reduced a total circuit area by using transmission lines instead of the bulky inductor for the general impedance matching. The proposed power amplifier showed the highest power gain of 26.8dB, the lowest power consumption of 45mW, the smallest chip area of 0.152mm², the highest power-added efficiency of 17.5% and the highest saturated output power of 19.5dBm as compared to recently research results.

Design of Low-Power 24 ㎓ CMOS Low Noise Amplifier

Seok-Ho Noh(노석호),Jee-Youl Ryu(류지열) 제어로봇시스템학회 2021 제어·로봇·시스템학회 논문지 Vol.27 No.11

In this paper, we present a low-power 24 ㎓ CMOS LNA (Low Noise Amplifier) for automotive collision avoidance radar. The proposed circuit was fabricated using the 65-nm RF CMOS technology and powered by a 1.2 V supply. To decrease the power consumption and increase the voltage gain, a cascode scheme was implemented in this circuit, and it was optimized to decrease the noise figure. Compared to the recently reported LNA, our proposed LNA showed the lowest power consumption and noise figure of 4.59 ㎽ and 2.98 ㏈, respectively, with a high voltage gain of 24.3 ㏈. Additionally, it was designed with the smallest chip area of 0.6×0.6 ㎟ and a core cell of 0.31×0.35 ㎟ without pads.