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Improvement of the Transconductance in a LDMOS Transistor with Dual Gate Oxide
나기열,김영석,Ki-Ju Baek 한국물리학회 2008 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.52 No.4
In this paper, we propose a lateral double diffused metal-oxide-semiconductor transistor (LDMOST) with dual gate oxide (DGOX) in order to improve the transconductance (gm). For the proposed LDMOST, the gate oxide on the source side is thicker than that on the drain side. The difference in the gate oxide thickness at the middle of the channel makes the threshold voltage variation lateral. This variation causes an abrupt channel potential distribution and enhances the lateral electric field. Therefore, the gm of the proposed device is improved. The proposed LDMOST was fabricated using a complementary metal-oxide-semiconductor (CMOS) process. The experimental results showed that the proposed LDMOST gave about a 52.5% improved maximum gm at the triode region compared to the conventional LDMOST. In addition, the drain-current-driving capability and the on resistances (RON) under the same bias conditions improved by about 41.7% and 13.4%, respectively. A two-dimensional device simulation was also performed to gain physical insight into the proposed LDMOST.
이중 일함수 게이트 구조를 갖는 CMOS 소자의 전기적 특성
나기열(Kee-Yeol Na),신윤수(Yoon-Soo Shin),김영식(Young-Sik Kim),이광규(Kwang-Kyu Lee),최홍규(Hong-Kyu Choi),김성준(Sungjoon Kim),김영석(Yeong-Seuk Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (gm) and drain conductance (gds) characteristics. For a n-channel metal-oxide-semiconductor field effect transistor (MOSFET) device, the poly-silicon gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-silicon gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved gm and gds over conventional single work function gate devices.
게이트와 드리프트 영역 오버랩 길이에 따른 LDMOST 전력 소자의 전기적 특성
하종봉,나기열,조경록,김영석,Ha, Jong-Bong,Na, Kee-Yeol,Cho, Kyoung-Rok,Kim, Yeong-Seuk 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.7
In this paper the gate overlap length of the LDMOST is optimized for obtaining longer device lifetime. The LDMOSI device with drift region is fabricated using the $0.25\;{\mu}m$ CMOS Process. The gate overlap lengths on drift region are $0.1\;{\mu}m,\;0.4\;{\mu}m\;0.8\;{\mu}m\;and\;1.1\;{\mu}m$, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with gate overlap length of $0.4\;{\mu}m$ showed the longest on-resistance lifetime, 0.02 years and breakdown voltage of 22 V and on-resistance of $23\;m\Omega{\cdot}mm^2$.
Suppression Techniques of Subthreshold Hump Effect for High-Voltage MOSFET
백기주,나기열,박정현,김영석 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.5
In this paper, simple but very effectivetechniques to suppress subthreshold hump effect forhigh-voltage (HV) complementary metal-oxidesemiconductor(CMOS) technology are presented. Two methods are proposed to suppress subthresholdhump effect using a simple layout modificationapproach. First, the uniform gate oxide method isbased on the concept of an H-shaped gate layoutdesign. Second, the gate work function controlmethod is accomplished by local ion implantation. Forour experiments, 0.18 μm 20 V class HV CMOStechnology is applied for HV MOSFETs fabrication. From the measurements, both proposed methods arevery effective for elimination of the inverse narrowwidth effect (INWE) as well as the subthreshold hump
0.25 μm 표준 CMOS 로직 공정을 이용한 Single Polysilicon EEPROM 셀 및 고전압소자
신윤수,나기열,김영식,김영석,Shin, Yoon-Soo,Na, Kee-Yeol,Kim, Young-Sik,Kim, Yeong-Seuk 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.11
For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.
Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications
백기주,나기열,김영석 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.5
This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide- semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (RON) and 50% drain conductance (gds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.
SOI 기판을 이용한 Thermal Probe 어레이 제작 및 특성 평가
조주현,나기열,박근형,이재봉,김영석,Cho, Ju-Hyun,Na, Kee-Yeol,Park, Keun-Hyung,Lee, Jae-Bong,Kim, Yeong-Seuk 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.11
This paper reports the fabrication and characterization of $5\;\times\;5$ thermal cantilever array for nano-scaled memory device application. The $5\;\times\;5$ thermal cantilever array with integrated tip heater has been fabricated with MEMS technology on SOI wafer using 7 photo masking steps. All single-level cantilevers have a diode in order to eliminate any electrical cross-talk between adjacent tips. Electrical measurements of fabricated thermal cantilever away show its own thermal heating mechanism. Thermal heating is demonstrated by the reflow of coated photoresist on the cantilever array surface.
Self-Cascode Structures Using Optional devices in Standard CMOS Technology
백기주,나기열,김영석 한국과학기술원 반도체설계교육센터 2016 IDEC Journal of Integrated Circuits and Systems Vol.2 No.1
This paper describes two possible configurations of an asymmetric-VTH self-cascode (SC) structure using optional devices in a 0.18-μm standard CMOS process. Standard CMOS technologies offer optional devices for a range of circuit design solutions, such as zero threshold voltage (ZVT) MOSFETs and thick gate oxide input/output (I/O) MOSFETs. In this paper, ZVT and I/O MOSFETs were implemented in the asymmetric-threshold voltage (VTH) self-cascode (SC) structures. These asymmetric-VTH SC structures with optional devices and a two-stage operational amplifier (OPAMP) using these SC structures were fabricated and evaluated. As a result of single device level evaluation, the SC with ZVT MNOSFET device showed improved output resistance as well as transconductance than the conventional single MOSFETs. From measurements of the fabricated two-stage OPAMP, the OPAMP with ZVT-SC device showed higher DC gain, faster slew rate, and higher unity-gain frequency.