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멀티비트 리코딩 병렬 승산기의 최적설계를 위한 면적-시간 복잡도 분석
김득경,신경욱,이용석,이문기 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.5
The usual approach for desinging a fast multiplier involves finding a way to quickly add up all the partial products, based on parital product recoding scheme and carry-save addition. This paper describes theoretical medels for area and time complexities of Multibit Reconding Paralle Multiplier (MRPM), which is a generalization of the modified Booth recoding scheme. Based on the proposed models, time performance, hardware requirements and area-time efficiency are analyzed in order to determine optimal recoding size for very large scale integration (VLSI) realization of the MRPM. Some simulation results show that the MRPM with large multiplier and multiplicand size has optimal area-time efficiency at the recoding size of 4-bit.
4-비트 리코딩 기법을 이용한 64-b x 67-b 병렬 승산기 설계
김득경,신경욱 金烏工科大學校 1994 論文集 Vol.15 No.-
This paper describes a design of 67-b parallel mutiplier using 4-bit recoding scheme. The multiplier supports both signed integer and unsigned integer, and operates in 2-stage pipelined manner. By adopting the 4-bit recoding scheme, which is an extension of the modified Booth algorithm (MBA), it requires only 22 partial products to be added, as compared with 32 partial products in the MBA. In order to reduce hardware complexity and to obtain better interconnect regularity, we utilize an optimized 4 : 2 carry-save adder (CSA) tree structure with the sign vector concept devised in this paper. The designed multiplier is modeled and verified using Verilog hardware description language (HDL). The multiplier can be used as a high-performance multiplier core for the arithmetic unit of microprocessors and general-purpose digital signal processors.
신현우,김천호,김득경,신창호,신경욱 國立金烏工科大學校附設生産技術硏究所 1994 産業技術開發硏究 Vol.10 No.-
The paper describes a CMOS analog circuit design tool, K_ACD(Kumoh_Analog Circuits Designer), and design results. The K_ACD was developed for automatic design of fundamental analog circuit blocks such as comparator, unbuffered OP AMP, and buffered OP AMP. For given specifications and process parameters, it computes bias currents, transistor sizes, voltage gain, and power dissipation, then SPICE simulations are automatically carried out. Some design examples show usefulness of the K_ACD in analog circuit designs.