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임베디드 SRAM의 Built-in Access Time 측정 회로 설계
신우철(Woocheol Shin),백경일(Kyungil Baek),정현섭(Hyunsub Jung),여정현(Junghyun Yo),권건태(Geuntae Kwon),이윤종(Yoonjong Lee) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.11
In this paper, we propose the built-in digital logic architecture and method for measuring the access time of embedded SRAMs. The proposed built-in architecture for access time measurement can be designed with only CMOS STD cell libraries and implemented using the auto placement and route techniques, which enables the proposed architecture to be applied in other process technologies. The built-in architecture makes it possible to measure the access timing using automated method without human errors and additional errors from the external measurement equipment. The proposed architecture can measure the timing with the precision of tens of picoseconds by using an accurate delay control scheme. The function and timing of the proposed logic were verified using logic simulations and a silicon test chip with DongBu Hitek 0.13um process.
Fail-Safe IO의 Low Power 회로 Solution
이상목(Sang-Mok Lee),오영귀(Young-Gwi Oh),차재아(Jae-Ah Cha),정현섭(Hyun-Sub Jung),여정현(Jung-Hyun Yo),권건태(Geun-Tae Kwon),이윤종(Yoon-Jong Lee) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.11
This paper describes the method to prevent the leakage current and function fail at power-off of an Input and Output(I/O) pad, and suggests using circuit to control NMOS driver. This circuit is operated as sleep mode at power-on and operated as wake-up mode (fail-safe) at power-off. Thus NMOS driver is kept as cut-off, so that this solution enables to prevent the leakage current and function fail.