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8개 압저항 브릿지구조를 이용한 저 타축 감도 실리콘 가속도센서
徐熙敦,李榮泰,崔世崑 경북대학교 센서기술연구소 1995 센서技術學術大會論文集 Vol.6 No.1
A low off-axis sensitivity piezoresistive accelerometer has been presented. The off-axis sensitivity was reduced by arrangement of eight piezoresistors on two the beams. The structure and stress distribution of the accelerometer was optimized using FEM(finite element modeling) simulation. The dependence of sensitivity and resonance frequency were also simulated as a function of the beam length for a constant overall size(2000μm). Accurate thickness control of the beams was realized by the etch-stop techonology using SDB(silicon direct bonding) wafer SiO_(2) layer and RIE(reative ion etching) method. This method is relatively simple and very useful for fabrication of accelerometer.
다채널 바이오텔레미터 개발을 위한 전용 IC 및 시스템 제작
서희돈,박종대 대한전자공학회 1994 전자공학회논문지-B Vol.b31 No.8
Implantable biotelemetry systems are indispensable tools not only in animal research but also in clinical medicine as such systems enable the acquisition of otherwise unavailable physiological data. We present the manufacture of CMOS IC and its system for implantable multichannel biotelemeter system. The internal circuits of this system are designed not only to achieve as multiple functions and low power dissipation as possible but also to enable continuous measurement of physiological data. Its main functions are to enable continuous measurement of physiological data and to accomplish on-off power swiching of an implantable battery by receiving appropriate commanc signals from an external circuit. The implantable circuits of this system are designed and fabricated on a single silicon chip using $1.5\mu$m n-well CMOS process technology. The total power dissipation of implantable circuits for a continuous operation was 6.7mW and for a stand-by operation was 15.2$\mu$ W. This system used together with approriate sensors is expected to contribute to clinical medicine telemetry system of measuring and wireless transmitting such significant physiological parameters as pressure pH and temperature.
홍경호,김철우,서희돈 嶺南大學校工業技術硏究所 1992 연구보고 Vol.20 No.2
Multiplier is a very important arithmetic component which performs an essential function in many digital computing systems. In this paper, the flush multiplier is proposed, which each data bit is come in serially is multiplied by coefficient bits, and is capable of k-bits production in k clocks. The proposed multipliers are able to perform the parallel multiplication fast and area-efficiently, and they are faster then the parallel multiplier using some algorithm which has been known as very fast algorithm.
CMOS 표준 셀 설계와 계산기를 이용한 레이아웃에 관한 연구
서희돈 嶺南大學校 工業技術硏究所 1988 연구보고 Vol.16 No.1
This paper describes the CMOS standard cell library implemented sigle poly gate process with 5㎛ design rule, its placement strategy and its results of testing. This standard cell library contains total 10 cells of basic logic gates, double logic gates and input/output buffers. All of the cells were made to have the equal height of 28λ. Cell placement and floor-plan is based on the iterative pairwise interchange using the estiment total routing length as a figure-of-merit. The device parameter and electric charactristics of each cell were investigated in the test element group. As the testing results of Ring Oscillator, the average delay time for inverter was 1.8(ns).
Pattern data 고속처리용 양방향 Switching Network 설계
서희돈 嶺南大學校 工業技術硏究所 1990 연구보고 Vol.18 No.1
This paper describes design of bi directional switching network which is a new parallel processing concept of layout pattern data. This network is consist of x and y directional 16 bit barrel shifters. The barrel shifter is designed as 256 n channel MOS transister and made into physical layout according to 3μm designed rules. The proposed system has considerable high speed as compared with an existing parallel processing method or a sofware processing method.
서희돈,박차훈,양승학 영남대학교 공업기술연구소 2000 工業技術硏究所論文集 Vol.28 No.1
In this paper we describes a next generation electronic security-light and street-light that is controlled remotely by the pager system. Especially, the time in the system is equal to current time. The used protocol is POCSAG(Post Office Code Standardization Advisory Group). Because PSTN is applied practically in the developmented system, we improve a communication quality and minimize to equipment investment. We can minimize the manufacturing cost and the development cost in the manufacturing of light control system.