시스템 성능 향상을 위한 예측기법의 오퍼랜드 참조 캐쉬 분석

최승교 三陟大學校 2000 論文集 Vol.33 No.1

Computer system performance is increasing dominated by the latency and the bandwidth requirement of servicing operand reads. However they are not easily supported by the conventional hierachial memory structure that is the typical technique to minimize the performance gap between a processor and memory subsytem. To solve this problem, we analyze various operand referncing characteristics of RISC based workload which is traced during benchmark programs. Through the trace-driven simulation of benchmark programs, the performance improvement by the proposed operand prediction cache structures is analyzed. The operand reference prediction cache with 512 entries shows the prediction accuracy of 91%, the prefetach rate of 43%, on average.

사용자 요구사항 정의를 위한 OLAP View의 제안 및 활용

최승교,박종모,Choi, Sung-Kyo,Park, Jong-Mo 한국정보처리학회 2004 정보처리학회논문지D Vol.11 No.4

OLAP 시스템은 사용자가 다양한 각도에서 정보에 접근하여 대화식으로 정보를 분석할 수 있는 의사결정 지원 시스템이다. 그러나 기존 OLAP 시스템의 구축방법은 사용자의 잦은 요구사항의 변경에 따라 시간과 비용이 증가하는 비효율성을 가진다. 본 연구에서는 OLAP 시스템의 기존 구축과정이 갖는 문제점을 분석하여, 사용자의 요구사항에 효율적으로 대응할 수 있도록 스타 스키마에 기반을 둔 프로토타이핑 OLAP View를 제안한다 제안 기법은 S 쇼핑몰의 구현 사례를 통해 사용자의 요구사항을 정확히 파악하여 OLAP의 구축 전략 수립이 가능하고, 데이터에 대한 이해와 정확한 파악이 가능하게 됨을 보인다. OLAP View를 사용함으로 OLAP 시스템 구축에 필요한 시간과 비용을 줄일 수 있다. An OLAP system is the decision support tool with which a user can analyze the information interactively in the various aspects. However, the traditional existing construction of an OLAP system has the inefficiency problem of increasing the time and cost caused by the frequent changes of the users requirements. In this paper, we analyse existing construction procedure of OLAP systems and propose a prototyping OLAP View based on the star schema which can help and guide the designer In supporting efficiently of users requirements. Through an implementation of S shopping mall using the OLAP View, we show that our proposal is able to support OLAP construction strategy and provide accurate understanding of data resources. With an OLAP View, we can reduce the required time and cost of implementing OLAP system.

Reduced Instruction Set Computer System 특성에 관한 연구

최승교 三陟大學校 1995 論文集 Vol.28 No.1

Various kinds of computer systems based on Reduced Instruction Set Computer concept have been announced and are becoming popular computer architectrue technologies today. But still there are lots of contentions on RISC definitions. In this paper, the technologies from RISC have been compared with those of CISC, and are seriously evaluated if they are the real key points for defining RISC concept. among the RISC technologies, Register File, Address Mode, Memory Access techniques can be also applicable to CISC, and they caused considerable performance speed-up either. Conclusively Those techniques can not be acceptable as unique technologies for RISC.

Cache Momory의 성능 향상을 위한 방법연구

최승교 三陟大學校 1999 論文集 Vol.32 No.1

As the performance of CPU improves rapidly, the performance gap between CPU and memory is getting bigger. Thus it is very important to construct a highly efficient cache memory in a high-performance system. In this paper, we prepose a path balancing technique to help match the delays of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a desigh that provides higher performance. Performance evaluation using both TPC-C and SPEC92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache designs. For TPC-C, improvements in the range of 6% to 28% are possible

VLSI 의 효율적인 Layout 설계 및 배치 Algorithm에 관한 연구

최승교 三陟大學校 1997 論文集 Vol.30 No.1

In a hierarchical VLSI Layout Design, Floor Plan is effectively used in placement of arbitrary size modules. In this paper, initial floor plan algorithm and new placement algorithm using relax is proposed. When various constraint conditions between the arbitrary size modules are provided, initial solutions are obtained using simplex method and among these are selected the prime solutions using implied relation. In order to reduce the space within the module, an effective placement improve algorithm which rotate and shift the modules within the chip using relax digraph method is proposed. Adopting these to various situations seeing the reduce of length, excess area, total area the effectiveness of these algorithm is showed.

혼합 예측기를 사용하는 효율적인 적재 명령어의 오퍼랜드 참조 기법

최승교,조경산,Choe, Seung-Gyo,Jo, Gyeong-San 한국정보처리학회 2000 정보처리논문지 Vol.7 No.7

As processor's operational frequency increases and processors execute multiple instructions per cycle, the processor performance becomes more dependent on the load operand referencing latency and the data dependency. To reduce the operand fetch latency and to increase ILP by breaking the data dependency, we propose a value-address hybrid predictor using a reasonable size prediction buffer and analyse the performance improvement by the proposed predictor. Through the extensive simulation of 5 benchmark programs, the proposed hybrid prediction scheme accurately predicts 62.72% of all loads which are 12.64% higher than the value prediction scheme and show its cost-effectiveness compared to the address predition scheme. In addition, we analyse the performance improvement achieved by the stride management and the history of previous predictions.

Solid State Disk를 이용한 Computer System의 성능 개선에 관한 연구

최승교 三陟大學校 1996 論文集 Vol.29 No.1

The slow speed of disk systems has been a performance bottle-neck considering recent progress in memory systems and parallel processing systems. Disk cache, a buffer holding recently-used portions of disk space contents may be a measure to enhance the system performance through reducing the number of disk accesses. But there is the problem of maintaining coherence on disk caches. Recently, owing to decreasing cost and reduced access time of NVM(Non-Volatile Memory) reliable as well as fast instrumentation of disk cache is possible. In this paper, implemation methods of disk cache using are presented and their performance is evaluated with a simulation method.

동시 Buffering 기법을 이용한 핸드오버 성능개선

최승교,Choi, Sung-Kyo 대한전자공학회 2005 電子工學會論文誌-TC (Telecommunications) Vol.42 No.7

최근 무선 인터넷의 수요가 기하급수적으로 증가함에 따라 Mobile IPv6가 제안되었으며, 이에 따른 핸드오버 지연을 줄이기 위한 빠른 핸드오버 기법이 제안되었다(IETF). 본 논문에서는 빠른 핸드오버 기법에서 발생하는 패킷의 손실 문제와 패킷의 비순서 문제를 해결하고 이로 인한 처리 지연을 줄일 수 있는 버퍼링 기법을 제안하였다. 또한 제안된 다양한 버퍼링 구조에 의한 빠른 핸드오버 기법의 성능 영향을 시뮬레이션을 통하여 분석하였다. 시뮬레이션을 통한 분석 결과, 제안된 버퍼링 기법은 패킷의 손실과 패킷의 비 순서를 해결하였고, 또한 기존 빠른 핸드오버 방식보다 버퍼링 기법은 최대 27$\%$정도 지연을 감소하였다. IETF proposed the Fast Handover mechanism to reduce the latency during which the mobile node is effectively disconnected from the Internet. However, the Fast Handover mechanism did not resolve packet loss and packet disordering problem. In this paper, we propose buffering mechanisms to resolve above problems in the Fast Handover mechanism. Though the simulation, we showed that packet loss and disordering problem have been absolutely resolved. In addition, our proposal reduced about 27$\%$ of the delay time by the buffering mechanism.

직업교육 방법의 개선방안 연구

최승교 三陟大學校 就業進路本部 2006 學生生活硏究 Vol.12 No.-

DHLF 연구 분석과 개선 방안에 대한 연구

최승교,이진영,주영삼 三陟大學校 1999 論文集 Vol.32 No.1

Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predictors combine a part of branch address with a fixed amount of global history of branch outcomes in order to make prediction. These predictors cannot perform uniformly well across all workloads because the best amount of history to be used depends on the code, the input data and the frequency of context switches. Consequently, all predictors that use a fixed history length are therefore unable to perform up to their maximum potential. Therefore propdsed a method-called DHLF-that dynamically determines the optimum history length during execution. But this method can not improve performance largely. We propose improving DHLF methods. Firstly, when history length is changed, it is directly set the history length to the one corresponding to the minimum in the misprediction history length. Secondly, we predict GAg predictor instead of gshare. Consequently, improving DHLF can achieve higher performance than existing DHLF.