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全粉愛,朴惠鯨,安光善 경북대학교 산업기술연구소 1993 産業技術硏究誌 Vol.21 No.-
In this paper, a SRAM for BIST with Boundary-SCAN Achitecture is designed, and simulated. The designed SRAM consists of Address Generator, Pseudo-Random Pattern Generator, Parallel Signature Analysor, TAP controller, Instruction Register, BYPASS Register. The simulation is satisfied with BYPASS, SAMPLE/PRELOAD, RUNBIST instructions.