http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
김세호(Sea-Ho Kim),김철홍(Cheol-Hong Kim),김희석(Hi-Seok kim) 한국정보기술학회 2007 Proceedings of KIIT Conference Vol.2007 No.-
본 논문에서는 RTL레벨에서 적용 가능한 클록 게이팅을 이용한 ODC연산을 사용하여 저전력 마이크로 프로세서 설계를 하였다. ODC연산은 동기식 논리 시스템에서 데이터패스의 출력으로부터 레지스터까지 Don't Care 조건을 추정하여 저전력 설계에 적용 할 수 있다. 본 논문에서는 ODC 연산의 결과를 이용하여 마이크로프로세서의 메모리 블록 및 레지스터파일에 적용하였다. 실험 결과 ODC연산적용 전과 비교하여 40%정도의 소비전력 감소결과를 구하였다. In this paper, a sample design of Micro processor and using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in digital system. Using modified this value, this paper shows the results of reduce consumption power due to controlling clock that was supplied at registers and memory block in Micro-processor. In Experimental results, ODC computation Method reduce dynamic power reductions of around 40%.
김세호(Sea-Ho Kim),양현미(Hyeon-Mi Yang),김희석(Hi-Seok Kim) 한국정보기술학회 2009 한국정보기술학회논문지 Vol.7 No.2
This paper presents a clock-gating method to reduce power consumption for the data-path of RISC core and Interface blocks through instruction decoding step. The proposed method has effectively controlled the clock switching dissipation by adopting clock-gating to the clock of memory blocks and the control signal of main controller. We have also exploited ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the I/O ports, Interrupt blocks, and Timer block in order to design the low-power interface blocks. In experimental results, the proposed Clock-gating method reduce dynamic power saving up to 38.4% comparing to those of RISC controller which is not adopted clock gating.
김세호(Sea-Ho Kim),김희석(Hi-seok kim) 한국정보기술학회 2008 한국정보기술학회논문지 Vol.6 No.2
In this paper, we have presents a modified clock gating block which is transformed from the previous clock gating block using ODC(Observability Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL) and applied practically to conventional micro-processor for low power design. Our modified clock gating block can be more reduced the power dissipation since it controls the clock in a bit of the register blocks comparing to the previous clock gating block. The presented clock gating block also applied to the register block which have a lot of power dissipation and the data bus blocks, ALU block, other several blocks additionally. Experimental results shows that our clock gating method more reduces dynamic power dissipations of around 46% comparing to those of the results of experiment which is not used ODC computation.
김세호(Sea-Ho Kim),양현미(Hyeon-Mi Yang),송우영(Woo-Young Song),김희석(Hi-Seok Kim) 한국정보기술학회 2009 Proceedings of KIIT Conference Vol.2009 No.-
MP3 디코더/인코더에 사용되는 Modified Discrete Cosine Transform(MDCT)/Inverse MDCT(IMDCT)을 DCT기반의 알고리즘을 사용하여 저전력으로 구현한다. MDCT/IMDCT의 계산과정은 MPEG audio layer3에서 가장 중요시 되며 디코딩/인코딩 시 가장 많은 연산량을 가진다. 따라서 본 논문에서는 MDCT/IMDCT의 공통 블럭을 사용하여 효율 적인 MDCT/IMDCT를 하드웨어로 구현 하였다. xilinx FPGA에 합성한 결과 94㎒의 동작 주파수로 합성된 것을 확인 하였다. In this paper, we have proposed the Modified Discrete Cosine Transform(MDCT)/Inverse MDCT(IMDCT) in MPEG audio layer 3 to a FPGA. The computation process of the MDCT/IMDCT is most intensive in MPEG audio layer 3. Therefore, this paper implemented an efficient IMDCT/MDCT using common operation block As the result to our experimental design, the MDCT/IMDCT are operated in 94㎒ on a XLINX-FPGA chip.
박근식(Sea-Ho Kim),김세호(Deun-Sik Park),김희석(Hi-Seok Kim) 한국정보기술학회 2010 Proceedings of KIIT Conference Vol.2010 No.-
본 논문에서는 RTL레벨에서 적용 가능한 Clock Gating을 이용한 ACG를 사용하여 저전력 UART 설계를 하였다. ACG는 순차회로인 FSM(Finite State Machine)구조에서 낭비되는 전력을 Don't Care 조건을 이용하여 줄였다. 실험 결과 ACG 적용 전과 비교하여 전력 소비가 약 30% 정도 감소하였다. In this paper, a sample design of UART using ACG(Adaptive Clcok Gating) that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ACG reduced the waste of the electric power from FSM structure of the Sequential logic by using Don't care condition. In Experimental results, ACG reduce power reduction of around 30% respectively.
박정호(Jeong-ho Park),고원기(Won-ki Ko),김세호(Sea-ho Kim),김희석(Hi-seok Kim) 한국정보기술학회 2011 Proceedings of KIIT Conference Vol.2011 No.5
본 논문에서는 열차 제어장치(ATC:Automatic Train Control)에 사용되고 있는 통신방식인 FSK 및 MSK 반송주파수를 소프트웨어로 제어 가능하도록 설계하고 이를 ASIC으로 구현하였다. 구현한 변조기는 FSK 동작에서 M 2, 4 8-ary를 지원하고 가우시안 필터의 BT를 조절할 수 있도록 설계하였다. 설계한 변조기는 VHDL로 설계하고 TSMC 0.18㎛ 공정을 이용하여 ASIC으로 구현하였다. In this paper, the train control (ATC: Automatic Train Control) is used for expression, communication method and carrier frequency, FSK, and MSK communication system is designed to be controlled by the software, and it was implemented by ASIC. Implementation of the FSK modulator operating in the M 2, 4 8-ary to support BT's control Gaussian filter was designed. Designed modulator is designed in VHDL using TSMC 0.18㎛ process was implemented by ASIC
박정호(Jeong-ho Park),고원기(won-ki Go),김세호(Sea-ho Kim),허재영(Jae-young Heo),김희석(Hi-seok Kim) 한국정보기술학회 2012 Proceedings of KIIT Conference Vol.2012 No.11
본 논문에서는 3D 영상 처리를 위해 스테레오 카메라에서 입력되는 두 영상 간의 물리적인 틀어짐을 보정하기 위해 하드웨어 알고리즘을 제안한다. interpolation보정기법을 사용하지 않고 제안된 알고리즘을 (sin, cos table Rotation) 사용하여 하드웨어로 설계 및 구현 하였다. 설계된 시스템의 결과는 Visual Studio 2008 MFC로 선 검증하여 동일한 결과를 확인하여 신뢰성을 입증하였다. In this paper, in order to compensate for the physical input from a stereo camera for 3D image processing between two images. Perfect hardware algorithm is proposed. using hardware interpolation calibration technique without using the proposed algorithm (sin, cos table Rotation) has been designed and implemented. Results of a system designed to verify the line with Visual Studio 2008 MFC was confirmed by the results of the same proven reliability.
Hi-Seok Kim(김희석),Sea-Ho Kim(김세호) 한국정보기술학회 2013 한국정보기술학회논문지 Vol.11 No.9
With the advance of image processing and computer vision, the stereo vision system with two cameras has become the research of interest in many areas since its ability to realize the depth information is similar to human vision. Depth map algorithm allows camera system to estimate depth. It is a computation intensive algorithm can be implemented with high speed on hardware due to the parallelism property. In this paper, by analyzing digital image stabilization (DIS) algorithms, we propose an efficient disparity estimation architecture, which combines gray-scaled projection and Affine transformation model. We develop the architecture by describing the various computation units in hardware description language (Verilog) and synthesizing the design into a FPGA. The synthesis and experimental results for three video test images show that the proposed hardwired architecture is better than traditional sum of absolute difference (SAD) architecture, which based on block matching algorithm in terms of frame rate (frame/sec) while keeping the competitive PSNR results.
이원표(Won-Pyo Lee),김세호(Sea-Ho Kim),윤달환(Dal-Hwan Yoon),김희석(Hi-Seok Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
In this paper, we design UART using ODC computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is began at point that estimate the value considering Don’t Care Conditions from output of datapath to registers using elk in system. Using modified this value, we reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 30%.