Analysis of Oxide Thickness Dependent Threshold Voltage of Asymmetric DGMOSFET

Hakkee Jung 한국정보통신학회 2014 2016 INTERNATIONAL CONFERENCE Vol.6 No.1

The threshold voltage of asymmetric double gate(DG) MOSFET has been analyzed for top and bottom gate oxide thickness using Gaussian doping profiles in channel. The asymmetric DGMOSFET is four terminal device to be able to bias different top and bottom gate voltage respectively. The threshold voltage is defined as the top gate voltage when drain current is 10<SUP>-7</SUP> A per unit channel width in the subthreshold region, given the constant bottom gate voltage. The threshold voltage for asymmetric DGMOSFET has been investigated, using our threshold voltage model for the change of top and bottom gate thickness. As a result, we know the threshold voltage has greatly changed for top and bottom gate oxide thickness, and the changing trend has been influenced on channel length and thickness.

Threshold Voltage Dependence on Bias for FinFET using Analytical Potential Model

Jung, Hak-Kee The Korea Institute of Information and Commucation 2010 Journal of information and communication convergen Vol.8 No.1

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

문턱전압 폐곡선을 이용한 AC PDP에서 인가전압에 의한 기입방전 특성의 연구

박승섭(Seung Seob Park),조병권(Byung-Gwon Cho) 한국정보기술학회 2020 한국정보기술학회논문지 Vol.18 No.2

The characteristics of the write discharge in the AC plasma display panel are determined by the sum of the wall voltage and the applied voltage formed inside the cell. If the applied voltage is increased under the high wall voltage condition, since the voltage is higher than the total voltage at which the discharge is generated in the cell, the misfiring discharge occurs in the unwanted cell. Therefore, as the total voltage generated inside the cell should be the same, the method of reducing the wall voltage and increasing the applied voltage is proposed. In this study, the write discharge characteristics of the applied voltage when the applied voltage was lower than the wall voltage and high were measured. The applied and the wall voltages were measured using the threshold voltage closed curve. As a result, the write discharge time can be shortened from 1.5 to 1.15μs when the applied voltage is higher than the wall voltage.

Analysis of Flat Band Voltage Dependent Breakdown Voltage for Sub-10 nm DGMOSFET

Hakkee Jung,Ohshin Kwon 한국정보통신학회 2017 2016 INTERNATIONAL CONFERENCE Vol.9 No.1

A model for the flat band voltage dependent breakdown voltage of sub-10 nm doublegate MOSFETs (DGMOSFETs) is proposed in this paper. Flat band voltage of gates is process dependent parameter by unintended process variables and uncertainties. Since variation of flat band voltage significantly effects on current-voltage characteristics, breakdown voltage depends on flat band voltage. Since avalanche is not occurred in sub- 10 nm DGMOSFETs, breakdown by punch-through effect arises from lowering of potential energy emerges even in the region of low drain voltage. The drain breakdown voltage becomes very small with dramatic down scaling due to abrupt increasing of tunneling current. The new model is used to investigate the flat band voltage dependent breakdown voltage with parameters of channel dimension and top/bottom oxide thickness of sub-10 nm DGMOSFET. The breakdown voltage is decreased with reduction of channel length and flat band voltage and increase of channel thickness. The breakdown voltage is varied for top/bottom gate oxide thicknesses.

X-ray 이미지 센서용 싱글 픽셀 포톤 카운터 설계

백승면,김태호,강형근,전성채,진승오,허영,하판봉,박무훈,김영희,Baek, Seung-Myun,Kim, Tae-Ho,Kang, Hyung-Geun,Jeon, Sung-Chae,Jin, Seung-Oh,Huh, Young,Ha, Pan-Bong,Park, Mu-Hun,Kim, Young-Hee 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.2

본 논문에서는 디지털 의료 영상 및 진단 분야 그리고 산업용으로도 활용 가능한 싱글 포톤 계수형 영상센서를 $0.18{\mu}m$ triple-well CMOS(Complementary Metal Oxide Semiconductor) 공정을 사용하여 설계하였다. 설계된 Readout 칩용 싱글 픽셀은 디지털 X-ray 이미지 센서모듈을 간단화 하기 위해 단일 전원전압을 사용하였으며, Preamplifier의 출력 전압인 signal voltage(${\Delta}Vs$)를 크게 하기 위해 Folded Cascode CMOS OP amp를 이용한 Preamplifier를 설계하였으며, 기존의 Readout 칩 외부에서 인가하던 threshold voltage를 Readout 칩 내부에서 생성해 줄 수 있도록 Externally Tunable Threshold Voltage Generator 회로를 새롭게 제안하였다. 그리고, Photo Diode에서 발생하는 Dark Current Noise를 제거하기 위한 Dark Current Compensation 회로를 제안하였으며, 고속 counting이 가능하고, layout 면적이 작은 15bit LFSR(Linear Feedback Shift Resister) Counter를 설계하였다. A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

등가회로 모델에 의한 레이저다이오드의 누설전류 해석

최영규,김기래,Choi, Young-Kyu,Kim, Ki-Rae 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.2

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has tern designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed. 본 논문에서는 디지털 의료 영상 및 진단 분야 그리고 산업용으로도 활용 가능한 싱글 포톤 계수형 영상센서를 $0.18{\mu}m$ triple-well CMOS(Complementary Metal Oxide Semiconductor) 공정을 사용하여 설계하였다. 설계된 Readout 칩용 싱글 픽셀은 디지털 X-ray 이미지 센서모듈을 간단화 하기 위해 단일 전원전압을 사용하였으며, Preamplifier의 출력 전압인 signal voltage(${\Delta}Vs$)를 크게 하기 위해 Folded Cascode CMOS OP amp를 이용한 Preamplifier를 설계하였으며, 기존의 Readout 칩 외부에서 인가하던 threshold voltage를 Readout 칩 내부에서 생성해 줄 수 있도록 Externally Tunable Threshold Voltage Generator 회로를 새롭게 제안하였다. 그리고, Photo Diode에서 발생하는 Dark Current Noise를 제거하기 위한 Dark Current Compensation 회로를 제안하였으며, 고속 counting이 가능하고, layout 면적이 작은 15bit LFSR(Linear Feedback Shift Resister) Counter를 설계하였다.

The effect of interface-induced structural properties of the pentacene accumulation layer on the threshold voltage: Pentacene monolayer transistors

Elsevier Sequoia 2017 THIN SOLID FILMS - Vol.627 No.-

The effect of pentacene/gate dielectric interface-induced structural properties of a pentacene monolayer (ML) close to the SiO<SUB>2</SUB> gate dielectric on the threshold voltage in the field effect transistor (FET) and van der Pauw was addressed using atomic force microscopy and near edge X-ray absorption fine structure spectroscopy (NEXAFS). Our study reveals that large negative threshold voltage found in FET and van der Pauw devices is not closely correlated to the molecular orientation and the grain size of pentacene molecules in direct contact with the SiO<SUB>2</SUB> gate dielectric. In concluding our finding, NEXAFS results in the ultrathin pentacene film within the carrier accumulation thickness regime, characterized by Debye length, were correlated to the magnitude of the threshold voltage from field effect devices. Our work motivates finding and visualizing interface-induced structural properties that are directly correlated to the magnitude of the threshold voltage.

Design of an efficient RF-DC voltage multiplier for RF Energy Harvesting Applications

Danial Khan,Hamed Abbasizadeh,Zaffar Hayat Nawaz Khan,Truong Thi Kim Nga,Sang Yun Kim,Ho Cheol Ryu,Kang Yoon Lee 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.1

In this paper, a RF-DC voltage multiplier is presented to efficiently convert RF signals to DC voltages. The proposed circuit uses an internal threshold voltage cancellation (IVC) scheme with auxiliary block to reduce the threshold voltage of forward-biased transistors and minimizes the reverse leakage current of the reverse-biased by dynamically controlling the gate-source voltage of the transistors in the main rectification chain. The proposed circuit is designed in 0.18 um CMOS technology. A three-stage voltage multiplier results in a maximum power conversion efficiency (PCE) of 49.1% at input power level of 0 dBm and at frequency of 900 MHz. The proposed circuit produces an output voltage of 4.94 V at 50 KΩ load.

채널 폭에 따른 MOSFET 문턱전압 및 전류 변동성에 관한 시뮬레이션 분석

정인영(In-Young Chung),박찬형(Chan Hyeong Park) 대한전자공학회 2018 전자공학회논문지 Vol.55 No.6

짧은 채널 길이와 긴 채널 너비를 갖는 MOSFET은 너비 방향으로 불균일한 채널 불순물 농도를 갖게 되며, 이에 의해 너비 방향으로 각 지점에서의 MOSFET 채널은 서로 다른 값의 문턱전압을 갖게 된다. 본 논문에서는 넓은 폭의 MOSFET을 문턱전압이 정규분포의 변동성을 갖는 W/L=1인 단위 MOSFET의 병렬연결로 모델링하여 SPICE 모델 파라미터를 활용한 시뮬레이션 기법으로 폭의 길이에 따른 전류-전압곡선의 특성을 분석한다. 이 분석을 통해 MOSFET의 폭이 넓어질수록 문턱전압이 낮아지고 문턱전압 이하 영역에서의 전류곡선의 지수기울기가 감소하는 것을 파악한다. 또한 문턱전압 부근과 그 이하 영역에서 MOSFET 너비에 따른 전류의 분포를 예측함으로써 전류 매칭에 유리한 MOSFET의 크기와 바이어스 조건을 제시한다. 이러한 분석 결과는 문턱전압의 변동성을 잘 견디는 초저전압 동작 아날로그 회로의 설계에 유용하게 활용될 것으로 기대된다. Short-channel length and wide-channel width MOSFET’s have nonuniform channel doping density along the channel width, making local threshold voltage along the width different We develop a wide-width MOSFET model by the parallel connection of unit MOSFET of W/L=1 with its threshold voltage normal-distributed. The current-voltage characteristics with respect to the width are analyzed by simulation method employing SPICE model parameters. This analysis shows that the threshold voltage becomes lower and the slope of the logarithmic value of current over the gate voltage in subthreshold region decreases as the channel width increases. Furthermore, by predicting current distribution with respect to the width around the threshold voltage and in the subthreshold region, a MOSFET size and a bias condition are presented for optimal current matching. These analysis results are expected to be used for the ultralow-voltage analog circuit design which is robust against the variability of threshold voltage.

A Simple Technique to Improve the Output Voltage of the CMOS Dickson Charge Pump Circuit

Jirawath Parnklang,Nutchaya Kaewraungrit,Sittisak Chaisotthe 제어로봇시스템학회 2008 제어로봇시스템학회 국제학술대회 논문집 Vol.2008 No.10

This article is a design of Charge pump circuit, which used CMOS transistor for generated high output DC voltage from the low 0.9v, 1.2v and 1.5v input DC voltage. Circuits are based on Dickson charge pump when forward bias to the substrate of MOSFET transistor structure of each state, this have an affect on the output to increase higher voltage. This body biased concept demonstrates by simulation program PSPICE using MOSIS model BSIM3V3. circuit comprises of biased voltage to substrate of NMOS transistor in Charge pump circuit. The circuit used MOSFET transistor N-type, P-type coupled in series with the input voltage to generated voltage is 0, 0.1, 0.2, 0.3, 0.4 and 0.5 V interconnected to the substrate of the NMOS. Two - overlapping clock signal driving the charge pump at 50 MHz. The circuit proved in the article have shown that can be adjust the value of output voltage, with from normal voltage will increase to voltage be equal to 20%, as the value of biased voltage to body equal to 0.5V.