New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application

Yuseok Jeon,Sungil Bang 한국전자파학회JEES 2017 Journal of Electromagnetic Engineering and Science Vol.17 No.3

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

A Fast Locking Dual-Loop PLL with Adaptive Bandwidth Scheme

송윤귀(Youn-Gui Song),최영식(Young-Shig Choi) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.5

본 논문에서는 루프 대역폭을 조절하여 빠른 위상 고정 시간을 갖는 새로운 구조의 이중 루프 위상고정루프를 제안하였다. 위상고정루프가 out-lock 상태일 때는 채널 간격의 1/10보다 더 큰 대역폭을 갖도록 하였으며, in-lock 부근에서는 채널 간격의 1/10 보다 더 작은 좁은 대역폭을 갖도록 하였다. 제안된 위상고정루프는 표준 CMOS 0.35㎛ 공정으로 HSPICE를 이용하여 설계 하였다. 시뮬레이션 결과 PLL의 대역폭을 200㎑ 채녈 간격 보다 14배 크게 하여 80㎒의 주파수를 변화시키는데 50㎲의 빠른 위상고정 시간을 갖는 것으로 나타났다. A novel fast locking dual-loop integer-N phase locked loop (PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a 0.35㎛ CMOS process with a 3.3V supply voltage. Simulation results show the fast lock time of 50㎲ for an 80㎒ frequency jump in a 200㎑ channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

위상고정 시간이 빠른 새로운 듀얼 슬로프 위상고정루프

박종하(Jong-Ha Park),김훈(Hoon Kim),김희준(Hee-Jun Kim) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.5

본 논문은 고속 위상 고정이 가능한 새로운 듀얼 슬로프 위상고정루프를 제안한다. 기존의 듀얼 슬로프 위상고정루프는 각각 2개의 전하펌프와 위상 주파수 검출기로 구성되었다. 본 논문에서는 위상차에 따라 전하펌프의 전류를 조절해 하나의 전하펌프와 위상 주파수 검출기만으로 듀얼 슬로프 위상고정루프를 구현하였다. 제안된 회로는 0.35㎛ CMOS 공정 파라미터 값으로 HSPICE 시뮬레이션을 수행하여 회로의 동작을 검증하였다. 제안된 듀얼 슬로프 위상고정루프의 위상 고정 시간은 2.2㎲로 단일 슬로프 위상고정루프의 위상 고정 시간인 7㎲보다 개선된 결과를 얻었다. This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a 0.35㎛ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was 2.2㎲ and that of the single-slope phase-locke loop was 7㎲.

IoT 어플리케이션을 위한분수분주형 디지털 위상고정루프 설계

김신웅 한국전기전자학회 2019 전기전자학회논문지 Vol.23 No.3

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performsa divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noiseperformance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter(DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, aphase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock andreflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. Theproposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations. 본 논문은 2.4 GHz 대역의 IoT용 주파수합성기를 위한 이중-루프 구성의 서브-샘플링 디지털 PLL을 소개한다. PLL은 초기에 주파수 분주기를 사용하는 coarse locking을 수행하며, 이 후 최종적으로는 주파수 분주기를 사용하지 않는 서브-샘플링 방식의 fine locking loop로 스위칭하게 된다. DTC를 사용하여 양자화 에러 제거를 수행하며 이를 통해 특정 타이밍 범위를 갖는 고해상도 TDC를 사용함으로써 낮은 인-밴드 위상잡음 특성을 가질 수 있다. 본 논문에서는 또한 coarse loop와 fineloop간의 위상 오프셋을 제거하기 위한 보정 회로를 제안하였다. Coarse locking이 진행되는 동안 fine loop의 위상 에러를예측하고, 이를 다시 coarse loop에 보상함으로써 빠른 락킹 타임과 안정적인 동작을 확보하였다. 회로는 SystemVerilog 및Verilog 언어로 모델링 및 Register-Transfer Level (RTL) 수준으로 설계 되었으며 시뮬레이션을 통해 충분히 그 동작이 검증되었다.

저 전력 시스템을 위한 파워다운 구조를 가지는 이중 전하 펌프 PLL 기반 클록 발생기

하종찬,황태진,위재경,Ha, Jong-Chan,Hwang, Tae-Jin,Wee, Jae-Kyung 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.11

이 논문에서는 다중 동작 주파수를 갖는 고성능 저전력 SoC에 사용 가능한 광대역 입출력 주파수를 지원하는 프로그램머블 PLL 기반의 클록킹 회로을 제안하였다. 제안된 클록 시스템은 이중 전하펌프를 이용 locking 시간을 감소시켰고, 광대역 주파영역에서 동작이 가능하도록 하였다. 칩의 저 전력 동작을 위해 동작 대기모드 시에 불필요한 PLL 회로를 지속적으로 동작시키지 않고 relocking 정보를 DAC를 통해 보존하고 불필요한 동작을 억제하였고, 대기모드에서 빠져나온 후 tracking ADC(Analog to Digital Converter)를 이용하여 빠른 relocking이 가능하도록 설계하였다. 또한 프로그램머블하게 출력 주파수를 선택하게 하는 구조를 선택하여 저 전력으로 최적화된 동작 주파수를 지원하기 위한 DFS(Dynamic frequency scaling) 동작이 가능하도록 클록 시스템을 설계하였다. 제안된 PLL 기반의 클록 시스템은 $0.35{\mu}m$ CMOS 공정으로 구현하였으며 2.3V의 공급전압에서 $0.85{\mu}sec\~1.3{\mu}sec$($24\~26$사이클)의 relocking 시간을 가지며, 파워다운 모드 적용 시 PLL의 파워소모는 라킹 모드에 비해 $95\%$이상 절감된다. 또한 제안된 PLL은 프로그래머블 주파수 분주기를 이용하여 다중 IP 시스템에서의 다양한 클록 도메인을 위해 $81MHz\~556MHz$의 넓은 동작 주파수를 갖는다. This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies

Junghwan Yoo,Jae-Sung Rieh 한국전자파학회JEES 2017 Journal of Electromagnetic Engineering and Science Vol.17 No.2

This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84−122.61 GHz and 126.53−129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are −8.6 dBm and −10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. The measured phase noise of PLL1 is −59.2 at 10 kHz offset and −104.5 at 10 MHz offset, and the phase noise of PLL2 is −60.9 dBc/Hz at 10 kHz offset and −104.4 dBc/Hz at 10 MHz offset. The chip sizes are 1,080 μm × 760 μm (PLL1) and 1,100 μm × 800 μm (PLL2), including the probing pads.

PLL Equivalent Augmented System Incorporated with State Feedback Designed by LQR

Somsak Wanchana,Tawom Benjanarasuth,Noriyuki Komine,Jongkol Ngamwiwit 대한전기학회 2007 International Journal of Control, Automation, and Vol.5 No.2

The PLL equivalent augmented system incorporated with state feedback is proposed in this paper. The optimal value of filter time constant of loop filter in the phase-locked loop control system and the optimal state feedback gain designed by using linear quadratic regulator approach are derived. This approach allows the PLL control system to employ the large value of the phase-frequency gain Kd and voltage control oscillator gain K?. In designing, the structure of phase-locked loop control system will be rearranged to be a phase-locked loop equivalent augmented system by including the structure of loop filter into the process and by considering the voltage control oscillator as an additional integrator. The designed controller consisting of state feedback gain matrix K and integral gain kI, is an optimal controller. The integral gain kI related to weighting matrices q and R will be an optimal value for assigning the filter time constant of loop filter. The experimental results in controlling the second-order lag pressure process using two types of loop filters show that the system response is fast without steady-state error, the output disturbance effect rejection is fast and the tracking to step changes is good.

계통연계형 단상 인버터의 ZVRT(Zero Voltage Ride Through)를 위한 PLL 제어 전략

이태일,이경수 전력전자학회 2019 전력전자학회 논문지 Vol.23 No.3

Grid codes for grid-connected inverters are essential considerations for bulk grid systems. In particular, a low-voltage ride-through (LVRT) function, which can contribute to the grid system’s stabilization with the occurrence of voltage sag, is required by such inverters. However, when the grid voltage is under zero-voltage condition due to a grid accident, a zero-voltage ride-through (ZVRT) function is required. Grid-connected inverters typically have phase-locked loop (PLL) control to synchronize the phase of the grid voltage with that of the inverter output. In this study, the LVRT regulations of Germany, the United States, and Japan are analyzed. Then, three major PLL methods of grid-connected single-phase inverters, namely, notch filter-PLL, dq-PLL using an active power filter, and second-order generalized integrator-PLL, are reviewed. The proposed PLL method, which controls inverter output under ZVRT condition, is suggested. The proposed PLL operates better than the three major PLL methods under ZVRT condition in the simulation and experimental tests.

고속 저전압 위상 동기 루프(PLL) 설계

황인호(Hwang In Ho),조상복(Cho Sang Bock) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.4

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump) and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200㎒ to 1.1㎓ and have 1.7㎓/v of voltage gain. The proposed PLL is designed by using 0.l8um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25㎒, VCO output frequency is 800㎒ and lock time is 5us. It is evaluated by using cadence spectra RF tools.

외란에 강인한 새로운 구조의 3상 Phase-Locked Loop

裵炳烈(Byung-Yeol Bae),韓炳文(Byung-Moon Han),朴用熙(Yong-Hee Park),曺胤瑚(Yun-Ho Cho) 대한전기학회 2006 전기학회논문지 B Vol.55 No.1

PLL is a key item of power converter for power quality compensation and power flow control. This paper proposes a novel 3-phase PLL that is composed of ALC and PI controller. The operational principle was investigated through theoretical approach, and the performance was verified through computer simulations with MATLAB and experimental works with TMS320VC33 DSP board. The proposed 3-phase PLL shows accurate performance under the voltage disturbances such as sag, harmonics, phase-angle jump, and frequency change.