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Word2Vec과 가속화 계층적 밀집도 기반 클러스터링을 활용한 효율적 봇넷 탐지 기법
이태일,김관현,이지현,이수철 한국인터넷정보학회 2019 인터넷정보학회논문지 Vol.20 No.6
Numerous enterprises, organizations and individual users are exposed to large DDoS (Distributed Denial of Service) attacks. DDoS attacks are performed through a BotNet, which is composed of a number of computers infected with a malware, e.g., zombie PCs and a special computer that controls the zombie PCs within a hierarchical chain of a command system. In order to detect a malware, a malware detection software or a vaccine program must identify the malware signature through an in-depth analysis, and these signatures need to be updated in priori. This is time consuming and costly. In this paper, we propose a botnet detection scheme that does not require a periodic signature update using an artificial neural network model. The proposed scheme exploits Word2Vec and accelerated hierarchical density-based clustering. Botnet detection performance of the proposed method was evaluated using the CTU-13 dataset. The experimental result shows that the detection rate is 99.9%, which outperforms the conventional method. 수많은 기업체, 기관, 개인 사용자가 대규모 DDos(Distributed Denial of Service)공격에 의한 피해에 노출되고 있다. DDoS 공격은 좀비PC라 불리는 수많은 컴퓨터들과 계층적 지령구조를 좀비PC들을 제어하는 네트워크인 봇넷을 통하여 수행된다. 통상의 악성코드 탐지 소프트웨어나 백신은 멀웨어를 탐지하기 위해서 사전에 심층 분석을 통한 멀웨어 시그니처를 밝혀야 하며, 이를 탐지 소프트웨어나 백신에 업데이트하여야 한다. 이 과정은 방대한 시간과 비용이 소모된다. 본고에서는 인공신경망 모델을 이용하여 주기적인 시그니처 사전 업데이트가 필요 없는 봇넷 탐지기법을 제안한다. 제안하는 인공신경망 모델은 Word2Vec과 가속화 계층적 밀집도 기반 클러스터링을 활용한다. 제안기법의 봇넷 탐지성능은 CTU-13 데이터셋을 이용하여 평가하였다. 성능평가 결과, 분류 정확도 99.9%로 기존 방법에 비해 우수한 멀웨어 탐지율을 보인다.
Conventional CMOS 공정을 위한 GGNMOS Type의 ESD 보호소자의 TLP 특성 평가
이태일,김홍배,Lee, Tae-Il,Kim, Hong-Bae 한국전기전자재료학회 2008 전기전자재료학회논문지 Vol.21 No.10
In this paper, we deal with the TLP evaluation results for GGNMOS in ESD protection device of conventional CMOS process. An evaluation parameter for GGNMOS is that repeatability evaluation for reference device($W/L=50\;{\mu}m1.0\;{\mu}m$) and following factors for design as gate width, number of finger, present or not for N+ gurad -ring, space of N-field region to contact and present or not for NLDD layer. The result of repeatability was showed uniformity of lower than 1 %. The result for design factor evaluation was ; 1) gate width leading to increase It2, 2) An increase o( finger number was raised current capability(It2), and 3) present of N+ gurad-ring was more effective than not them for current sink. Finally we suggest the optimized design conditions for GGNMOS in evaluated factor as ESD protection device of conventional CMOS process.
계통연계형 단상 인버터의 ZVRT(Zero Voltage Ride Through)를 위한 PLL 제어 전략
이태일,이경수 전력전자학회 2019 전력전자학회 논문지 Vol.23 No.3
Grid codes for grid-connected inverters are essential considerations for bulk grid systems. In particular, a low-voltage ride-through (LVRT) function, which can contribute to the grid system’s stabilization with the occurrence of voltage sag, is required by such inverters. However, when the grid voltage is under zero-voltage condition due to a grid accident, a zero-voltage ride-through (ZVRT) function is required. Grid-connected inverters typically have phase-locked loop (PLL) control to synchronize the phase of the grid voltage with that of the inverter output. In this study, the LVRT regulations of Germany, the United States, and Japan are analyzed. Then, three major PLL methods of grid-connected single-phase inverters, namely, notch filter-PLL, dq-PLL using an active power filter, and second-order generalized integrator-PLL, are reviewed. The proposed PLL method, which controls inverter output under ZVRT condition, is suggested. The proposed PLL operates better than the three major PLL methods under ZVRT condition in the simulation and experimental tests.