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Analysis of surface plasmon polariton conversion coefficient in slit-groove structure
Park Yeonsang 한국물리학회 2022 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.80 No.9
A method for the analysis of finding the conversion efficiency of the surface plasmon polariton in slit-groove structures is proposed and studied. The conversion efficiency of the surface plasmon polariton can be determined by measuring the intensities of light scattered at the slit and groove positions. To verify the usefulness of the proposed method, two rigorous simulations based on the finite-difference time-domain method were executed and the simulation results compared with previously reported data. One was to mimic the far-field imaging experiment in slit-groove structure and the other was to calculate the conversion coefficient directly in a single scattering structure. The SPP conversion efficiencies obtained from the two simulations were approximately 0.232 and 0.220 respectively, and these agreed with the reported data. The suggested method can be used regardless of the shape of the plasmon-generation structure; therefore, it is expected to be useful in a wide range of experiments with different scattering structures.
Double-Layer antireflection coating design for semi-infinite one-dimensional photonic Crystals
Park, Yeonsang,Jeon, H. IEEE 2004 Journal of Lightwave Technology Vol.22 No.8
A theoretical formalism is established for double-layer (DL) antireflection coating (ARC) on a one-dimensional (1-D) photonic crystal (PC). Conventional DL-ARC for a bulk is equally applicable for a 1-D PC when the bulk substrate index is replaced with the optical admittance, which can be obtained from the electromagnetic Bloch waves of the infinite 1-D PC. Numerical calculations are performed for a model structure composed of GaAs and AlAs-oxide layers to confirm the validity of the theory. In terms of realization and practicality, this DL-ARC is expected to be superior to the single-layer version.
Optical slot antennas and their applications to photonic devices
Park, Yeonsang,Kim, Jineun,Roh, Young-Geun,Park, Q-Han De Gruyter 2018 Nanophotonics Vol.7 No.10
<P>We present optical slot antennas and their applications to photonic devices. We show that metallic nanoslots have the properties of a slot antenna by measuring the transmission spectra and far-field radiation patterns and then prove that they can be physically regarded as magnetic dipoles in the optical region. Additionally, we can generate directional radiations from optical slot antennas by adopting the geometry of radiofrequency Yagi-Uda antenna and properly adding auxiliary elements called reflectors and directors to a single slot antenna. We present two cases as the applications of optical slot antennas. One is the integration of slot antennas to plasmonic waveguides. This combination can be used as a basic unit for optical interconnection to free space and plasmonic via in multilayered plasmonic structures. The other is the integration of slot antennas to the electrode of light-emitting diodes (LEDs). Using slot antennas, we can control the polarization and direction of emissions from LEDs. Besides the above-mentioned two cases, we expect that optical slot antennas have possible applications to various photonic devices and can be essential elements in future integrated photonic circuits with nanometer scales.</P>
박민수 ( Min Su Park ),손현창 ( Hyeon Chang Son ),박연상 ( Yeonsang Park ) 충남대학교 기초과학연구원 2021 충남과학연구지 Vol.38 No.1
We have investigated experimentally electron beam lithography condition for the nanoscale patterning on a glass substrate. The condition for the nanoscale patterning using electron beam lithography are affected by various parameters such as the electron acceleration voltage, ebeam dose, and working distance etc. We investigated and reported the optimal condition of the nanoscale patterning on a glass substrate using the TESCAN MIRA3 in Center of Research Facilities.
윤연상(Yeonsang Yun),류광현(Kwang-Hyun Ryoo),박진섭(Jinsub Park),김용대(Yongdae Kim),한선경(Seonkyoung Han),유영갑(Younggap You) 한국정보보호학회 2004 정보보호학회논문지 Vol.14 No.4
본 논문에서는 IPSec 가속기의 성능분석 모델을 제안한다. 제안된 성능분석은 큐잉 모델링을 기반으로 하고 트래픽로드는 포아송 분포를 채택하였다. 성능분석 시 새로운 파라미터로 디코딩지연을 정의하여 시뮬레이션에 이용하였다. 제안된 모델을 이용하여 IPSec 가속장치인 BCM5820의 성능을 분석한 결과, 장비를 통해 실측된 결과와 15% 정도의 차이만을 나타내었다. 제안된 모델을 이용한 성능분석 결과는 IPSec 가속기의 최대성능을 유지하기 위한 서버내의 하드웨어들의 적합한 구조를 제시하고 나아가 고속 네트워크 컴퓨터의 통계적 설계공간탐색에 이용될 수 있다. This paper proposes an IPSec accelerator performance analysis model based a queue model. It assumes Poisson distribution as its input traffic load. The decoding delay is employed as a performance analysis measure. Simulation results based on the proposed model show around 15% differences with respect to actual measurements on field traffic for the BCM5820 accelerator device. The performance analysis model provides with reasonable hardware structure of network servers, and can be used to span design spaces statistically.
Chi-O Cho,Young-Geun Roh,Yeonsang Park,Jae-Soong I,전헌수,Beom-Seok Lee,Hye-Won Kim,Young-Ho Choe,Mingyu Sung 한국물리학회 2004 Current Applied Physics Vol.4 No.2-4
We propose a hybrid type of photonic crystal waveguide (PCW) structure, in which two-dimensional (2D) PCW is embedded in atwo one-dimensional (1D) PCW. This rather new PCW structure should be identical to a full three-dimensional PCW in itsfunctionality, but its fabrication is much simpler. Toward the realization of such an amenable PCW structure, an epitaxially grownGaAs/AlAs multilayer structure was successfully converted to an omnidirectional reector, suitable for the 1D photonic crystalstructure in the hybrid PCW. In terms of fabricating 2D-PCWs, we took a rather new approach instead of conventional electron-beam lithography. An air-bridge type of thin lm Si 2D-PCW was fabricated using a combined technique of holography andphotolithography. Optical characterizations revealed that the propagation loss of the waveguide fabricated such is comparable tothose of e-beam generating PCWs in the literature.
박진섭,윤연상,김용대,양상운,장태주,유영갑,Park Jinsub,Yun Yeonsang,Kim Young-Dae,Yang Sangwoon,Chang Taejoo,You Younggap 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.4
본 논문은 2004년 12월 국내 표준(KS)으로 제정된 ARIA 암호 알고리듬의 하드웨어 구조를 처음으로 제안하고 있다. ARIA 암호 알고리듬은 알려진 공격에 대하여 안전하며, Involution SPN (Substitution Permutation Network)으로써 구조적 효율성도 높다. 1 cycle/round 구조로 갖는 제안된 ARIA 구조는 회로 크기를 줄이기 위해 s-box를 듀얼 포트 롬과 배럴 로테이터를 채택한 고속의 라운드 키 생성기를 포함하고 있다. 제안된 ARIA는 Xilinx VirtexE-1600 FPGA를 사용하여 구현하였고, 1,490 slices와 16 RAM 블록을 사용해서 437 Mbps의 성능을 낸다. 설계된 ARIA 블록을 검증하기 위해서 영상 데이터를 암호화(복호화)하여 통신하는 시스템을 개발하였다. 설계한 ARIA는 IC 카드뿐만 아니라 데이터 저장이나 인터넷 보안 규격(IPSec, TLS)과 같은 많은 데이터를 고속 처리가 필요한 응용에 적용될 수 있다. This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.