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Bias and Device Optimization for 0.13-㎛ CMOS Low-Noise Amplifier Design
Ickhyun Song,Hakchul Jung,Hee Sauk Jhon,Hyungcheol Shin 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
A design approach for optimizing the performance of low-noise amplifiers is introduced. Figure of merit of LNAs which is composed of signal power gain, noise factor, and power consumption is used for evaluating the overall performance. Each factor is anayltically expressed in device parametes. By using this method, FoM of LNAs are maximized prior to the fabrication of circuits.
Optimization of cascode configuration in CMOS low-noise amplifier
Song, Ickhyun,Koo, Minsuk,Jung, Hakchul,Jhon, Hee-Sauk,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2008 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS - Vol.50 No.3
<P>In this paper, design consideration of the cascode configuration in low-noise amplifiers (LNA) using 0.13-μm CMOS technology is presented. Performance factors of LNAs such as signal power gain, noise factor, and power consumption are analytically expressed in device parameters from its small-signal equivalent circuit. The effect of the common-gate transistor in each performance factor is evaluated at the target frequency of 17-GHz ISM band. At this frequency, power gain and noise factor are degraded, which result from the common-gate transistor. Figure of merit of LNAs is also optimized. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 646–649, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23163</P>
Noise Interpolation of MOSFET in Moderate Inversion and Its Verification in Low Noise Amplifier
송익현(Ickhyun Song),구민석(Min Suk Koo),정학철(Hakchul Jung),이상훈(Sanghoon Lee),Shen Yehao,전희석(Hee Sauk Jhon),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
MOSFET noise in moderate inversion region is interpolated using two noise models in the regions of subthreshold and strong inversion. With these channel noise value, a CMOS low noise amplifier (LNA) operating in moderate inversion region is designed for verification and its noise characteristic is presented.
Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
JEON, Jongwook,SONG, Ickhyun,LEE, Jong Duk,PARK, Byung-Gook,SHIN, Hyungcheol The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.5
<P>In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65nm and 130nm CMOS technologies, respectively.</P>
2.4 GHz ISM-Band Receiver Design in a 0.18 <tex> $\mu{\hbox{m}}$</tex> Mixed Signal CMOS Process
Hee-Sauk Jhon,Ickhyun Song,In Man Kang,Hyungcheol Shin IEEE 2007 IEEE microwave and wireless components letters Vol.17 No.10
<P>This letter presents the design and measurement results of a fully integrated CMOS receiver front-end and voltage controlled oscillator (VCO) for 2.4 GHz industrial, scientific and medical (ISM)-band application. For low cost design, this receiver has been fabricated with a 0.18 mum thin metal CMOS process with a top metal thickness of only 0.84 mum. The receiver integrates radio frequency (RF) front-end (a single-ended low-noise amplifier (LNA) with on-chip spiral inductors and a double balanced down conversion mixer), VCO and local oscillation buffers on a single chip together with an internal output buffer. To obtain the high-quality factor inductor in LNA, VCO and down conversion mixer design, patterned-ground shields (PGS) are placed under the inductor to reduce the effect from image current of resistive Si substrate. Moreover, in VCO and mixer design, due to the incapability of using thick top metal layer of which the thickness is over 2 mum, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via arrays along the metal traces is adopted to compensate the Q -factor degradation. In this letter, the receiver achieves a conversion gain of 23 dB, noise figure of 8.1 dB and P1 dB of -20 dBm at 39 MHz with 21 mW power dissipation from a 1.8 V power supply. It occupies a whole circuit area of 2 mm<SUP>2</SUP>.</P>
Low power size-efficient CMOS UWB low-noise amplifier design
Jhon, Hee-Sauk,Song, Ickhyun,Jeon, Jongwook,Koo, MinSuk,Park, Byung-Gook,Lee, Jong Duk,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.51 No.2
<P>The design and measurement results of 3–5 GHz fully integrated ultra-wideband (UWB) CMOS LNA are presented. To boost the transconductance of the LNA and to reduce circuit area effectively, we eliminate a source degeneration inductor using resistive-feedback cascode structure. The implemented UWB LNA shows peak gain of 10.8 dB, more than 10 dB of input return loss, and a noise figure of 3.3–4.2 dB from 3 to 5.1 GHz with power dissipation of 14 mW. The input P1dB and input IP3 (IIP3) at 4 GHz are about −6 dBm and +4 dBm, respectively. For low cost, the LNA has been fabricated using a 0.18-μm thin metal CMOS process with top metal thickness of 0.84 μm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 494–496, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24104</P>
Kim, Junsoo,Lee, Jaehong,Song, Ickhyun,Yun, Yeonam,Lee, Jong Duk,Park, Byung-Gook,Shin, Hyungcheol IEEE 2008 IEEE transactions on electron devices Vol.55 No.10
<P> This paper presents a new extraction method for effective channel length <TEX Notation='TeX'> <TEX>$(L_{\rm eff})$</TEX></TEX> and source/drain series resistance <TEX Notation='TeX'><TEX>$(R_{\rm SD})$</TEX> </TEX> in ultrashort-channel MOSFETs using an iterative process, which is a modified channel resistance method (CRM). Although conventional methods for extracting <TEX Notation='TeX'><TEX>$L_{\rm eff}$</TEX></TEX> and <TEX Notation='TeX'><TEX>$R_{\rm SD}$</TEX></TEX>, such as the channel resistance and shift-and-ratio methods, are considered to be the most consistent techniques, they are not valid for shorter channel transistors, such as the total resistance <TEX Notation='TeX'><TEX>$(R_{\rm tot} = V_{\rm DS}/I_{\rm DS})$</TEX> </TEX> of MOSFETs, and do not scale proportionately with poly-gate length <TEX Notation='TeX'><TEX>$(L_{\rm poly})$</TEX></TEX>. This error results from the fact that these methods assume the effective mobility f<TEX Notation='TeX'><TEX>$(\mu_{\rm eff})$</TEX></TEX> of long- and short-channel transistors to be the same. This assumption inevitably lowers the accuracy of the extracted channel length in ultrashort-channel MOSFETs. Therefore, an improved CRM using an iterative procedure has been proposed. This iteration method takes into account the fact that mobility is degraded in shorter channel devices. By compensating for the mobility in long-channel devices, more accurate approximations for <TEX Notation='TeX'><TEX>$L_{ \rm eff}$</TEX></TEX> and <TEX Notation='TeX'><TEX>$R_{\rm SD}$</TEX></TEX> are extracted compared to conventional methods. </P>
Low Cost CMOS LNA Design Using On-Chip Size Efficient Inductors
전희석(Hee-Sauk Jhon),송익현(Ickhyun Song),윤여남(Yeonam Yun),구민석(Minsuk Koo),정학철(Hakchul Jung),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using size efficient inductors. We applied vertical shunt symmetric and helical inductor to match the input and output in 2.4 ㎓ CMOS LNA to reduce the circuit area. In this paper, the case of conventional LNA using asymmetric inductor, and that of ones using vertical shunt symmetrical and helical inductor with a relatively higher number of turns have been compared in order to present a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.
Jhon, Hee-Sauk,Jung, Hakchul,Koo, Minsuk,Song, Ickhyun,Shin, Hyungcheol Wiley Subscription Services, Inc., A Wiley Company 2009 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS - Vol.51 No.5
<P>A low supply voltage and highly linear subthreshold CMOS low noise amplifier (LNA) for 2.4 GHz wireless sensor network applications is presented in this letter. We applied multiple gated transistor (MGTR) technique in subthreshold region to compensate the linearity degradation of low supply cascode topology. Moreover, the feedback capacitor, C<SUB>f</SUB> is used to enhance the power gain of amplifier without additional dc-power dissipation. The proposed LNA has gain of 13.1 dB, noise figure (NF) of 3.8 dB, and −2.5 dBm IIP3 while dissipating only 0.49 mW from 0.7 V supply. The LNA has been designed using a 0.13 μm 1P8M standard CMOS process with top metal thickness of 3.3 μm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1316–1320, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24333</P>