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CMOS Integrated Multiple-Stage Frequency Divider with Ring Oscillator for Low Power PLL
안세혁,박주상,황인우,김남수 한국전기전자재료학회 2017 Transactions on Electrical and Electronic Material Vol.18 No.4
This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-lockedfrequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadbandand high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to dividethe frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure thefrequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of thedivider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 μm CMOS process. Simulationshows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for aninput frequency of 1.2 GHz, with a power consumption of 30 mW.
2차원 흐름해석모형의 매개변수 최적조합결정 자동화 알고리즘의 개발과 적용
안세혁,신은택,송창근,박성원,An, Sehyuck,Shin, Eun-taek,Song, Chang Geun,Park, Sungwon 한국수자원학회 2023 한국수자원학회논문집 Vol.56 No.-
Two-dimensional flow analysis, a fundamental component of hydrodynamics, plays a pivotal role in numerically simulating fluid behavior in rivers and waterways. This modeling approach heavily relies on parameters such as eddy viscosity and roughness coefficient to accurately represent flow characteristics. Therefore, combination of appropriate parameters is very important to accurately simulate flow characteristics. In this study, an automation algorithm was developed and applied to find the optimal combination of parameters. Previously, when applying a two-dimensional flow analysis model, former researchers usually depend on the empirical approach, which causes many difficulties in finding optimal variable values. Using the experimental data, we tracked errors according to the combination of various parameters and applied the algorithm that can determine the optimal combination of parameters with the Python language. The automation algorithm can easily determine the most accurate combination by comparing the flow velocity error values among the two-dimensional flow analysis results among the combinations of 121 (11×11) parameters. In the perspective of utilizing automation algorithm, there is an expected high utility in promptly and straightforwardly determining the optimal combination of parameters with the smallest error. 천수방정식 기반 흐름해석모형은 하천 및 수로에서의 흐름을 수평 2차원적으로 수치모의하는데 활용되며 매개변수인 와점성계수와 조도계수에 큰 영향을 받는다. 따라서 적절한 매개변수의 선택은 흐름특성을 정확하게 모사하기 위해 매우 중요하다. 본 연구에서는 2차원 흐름해석에 적용되는 매개변수의 최적조합을 찾기 위한 자동화 알고리즘을 개발하고 적용하였다. 기존연구에서 2차원 흐름해석모형을 적용하는 경우 매개변수의 선정에 있어 경험적인 방법을 사용하여 최적의 매개변수를 찾는데 어려움이 있었다. 따라서 본 연구에서는 실험결과를 활용하여 다양한 매개변수의 조합에 따른 오차를 추적하고, 매개변수의 최적조합을 결정할 수 있는 알고리즘을 Python 언어를 이용하여 개발하고 적용하였다. 자동화 알고리즘은 121(11×11)개의 매개변수 조합에 따른 2차원 흐름해석결과 중 유속모의결과의 오차값을 비교하여 가장 정확한 조합을 손쉽게 결정하도록 구성되었다. 오차가 가장 작은 매개변수의 최적조합을 자동화 알고리즘의 적용을 통해 신속하고 간단하게 결정할 수 있다는 측면에서 높은 활용가치가 있을 것으로 기대된다.
High-speed CMOS Frequency Divider with Inductive Peaking Technique
박정웅,안세혁,정혜임,김남수 한국전기전자재료학회 2014 Transactions on Electrical and Electronic Material Vol.15 No.6
This work proposes an integrated high frequency divider with an inductive peaking technique implemented ina current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop,and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupledn-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias isused for its high current driving capability and stable frequency response. The proposed divider is designed with0.18-μm CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL)circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In theoutput frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an inputfrequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.
옥상 헬리포트의 안전 확보를 위한 설치기준 제정에 관한 연구
신은택,안세혁,엄태수,송창근 한국방재학회 2022 한국방재학회논문집 Vol.22 No.4
Helicopters that can respond rapidly to medical accidents are used frequently on sites that require firefighting and medical services. Therefore, Korea recommends that high-rise buildings install heliports for easy evacuation through an alteration to the Building Act. However, because heliport installation laws are inconsistent with the specifications of each heliport on high-rise buildings being different, helicopter landing in emergencies may be hindered. This may result in failure to respond to an accident. To minimize complications, the International Civil Aviation Organization (ICAO) and the Federal Aviation Administration (FAA) determine helicopter take-off and landing regulations as well as heliport operations. This method minimizes human error in pilots and allows for the maintenance of facilities, minimizing technical errors. Therefore, this study investigates the current status of domestic rooftop heliports and attempts to derive measures that improve domestic legislation through comparison with overseas standards to identify higher standards. 사고 발생 시 신속하게 대응할 수 있는 헬리콥터는 소방, 의료 등 다양한 현장에서 빈번하게 사용되고 있다. 국내에서는 건축법에 따라 고층건물에 대피가 용이한 헬기장을 설치할 것을 권고하고 있다. 그러나 헬기장 설치법이 미비하고 고층건물의 헬기장마다 규격이 상이하므로 비상 시 헬리콥터의 착륙에 차질이 빚어져 사고대응에 지장이 초래될 수 있다. ICAO (International Civil Aviation Organization)와 FAA (Federal Aviation Administration)에서는 실제 문제를 최소화하기 위해 헬리콥터 이착륙에 대한 규정을 명확히 하고 운영 중인 옥상헬기장의 목적과 목적을 세분화하고 있다. 이 방법은 조종사의 인적오류를 최소화할 뿐만 아니라 시설의 유지관리를 용이하게 하여 기술적 오류를 최소화한다. 따라서 본 연구에서는 이러한 선진기준을 반영하여 국내 옥상헬기장의 현황을 조사하고, 이를 해외기준과 비교하여 국내법제 개선방안을 도출하고자 한다.