유한체 GF(2m)상의 셀 배열 병렬 승산기의 설계

성현경 ( Seong Hyeon Gyeong ) 한국정보처리학회 2004 정보처리학회논문지 A Vol.11 No.1

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF(2m) is presented in this paper. The presented cellular array parallel multiplier consists of three operation parts : the multiplicative MODOP are composed of the basic cells which are designed with AND gates and XOR gates. The IPOP is constructed by XORgates and D flip-flops. This multipliers is simulated by clock period 1us using PSpice. The proposed multiplier is designed by 24 AND gates, 32XOR gates operating time of MODOP using IPOP requires m Unittimes(clock times). Therefore total operating time is M 1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomial in the finite fields with very large m.

Bit code 연산에 의한 GF (2<SUP>m</SUP>) 상의 승산기 구성

성현경(Hyeon Kyeong Seong),강성수(Sung Su Kang),김흥수(Heung Soo Kim) 대한전자공학회 1986 대한전자공학회 학술대회 Vol.1986 No.12

레저용 카약 디자인 설계를 위한 사용자 의사결정 지원 시스템 개발

성현경(Hyeon-Kyeong Seong),최용석(Yong-Seok Choi),박병호(Byeong-Ho Park),박찬홍(Chan-Hong Park),임이영(Lee-Young Lim) 한국디지털콘텐츠학회 2014 한국디지털콘텐츠학회논문지 Vol.15 No.2

The change from people`s work-centered values to their leisure-centered values leads into the change in their life styles. In the circumstance, people`s participation into sports activities seems to be an important means to improve their quality of life. Along with the change of the times, more people take part in water leisure sports including kayak. As a result, peoples needs for various designs of water leisure goods are on the rise. In this sense, it is necessary to come up with strategies to actively respond to such a change. In this paper, we proposed a user decision-making support system for designing kayaks for leisure. Based on the previous studies and literatures and a questionnaire survey with consumers, it chose the sensitivity related to design. By conducting factor analysis and evaluation, it drew sensitivity and proposed kayak design layouts in the aspect of customer sensitivity preference. It is expected that the result of this study will be used not only for kayak design, but as a design guide for the equipment of water leisure sports, and will be applied for user-friendly design.

유한체 GF(2<SUP>m</SUP>)상의 기약다항식의 모든 계수가 1을 갖는 고속 병렬 승산기의 설계

성현경(Hyeon-Kyeong Seong) 한국컴퓨터정보학회 2013 韓國컴퓨터情報學會論文誌 Vol.18 No.2

본 논문에서는 유한체 GF(2<SUP>m</SUP>)상에서 모든 항에 0이 아닌 계수가 존재하는 기약 다항식을 이용한 두 다항식에 대한 승산 알고리즘을 제시하였으며, 제시된 승산 알고리즘을 이용하여 고속의 병렬 입-출력 모듈구조의 승산기를 설계하였다. 제시한 승산기의 구성은 ㎡개의 동일한 기본 셀들로 설계되었으며, 제시한 기본 셀은 2입력 XOR 게이트와 2입력 AND 게이트로 구성하였다. 셀에 래치를 사용하지 않았으므로 회로가 간단하며, 셀당 지연시간이 DA</SUB)+ DX</SUB)이다. 본 연구에서 제안한 승산기는 규칙성과 셀 배열에 의한 모듈성을 가지므로 m이 큰 회로의 확장이 용이하며 VLSI회로 실현에 적합할 것이다. In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF(2<SUP>m</SUP>), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed ㎡ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time DA</SUB)+ DX</SUB) per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

유한체 GF(3<SUP>m</SUP>)상의 고속 병렬 곱셈기의 설계

성현경(Hyeon-Kyeong Seong) 한국컴퓨터정보학회 2015 韓國컴퓨터情報學會論文誌 Vol.20 No.2

본 논문에서는 유한체 GF(3<SUP>m</SUP>)상에서 모든 항에 0이 아닌 계수를 갖는 기약 다항식에 대하여 m이 홀수 및 짝수인 경우 GF(3<SUP>m</SUP>)상의 곱셈 알고리즘을 제시하였으며, 제시한 곱셈 알고리즘을 이용하여 고속의 병렬 입-출력 모듈구조의 곱셈기를 설계하였다. 제시한 곱셈기의 구성은 (m+1)<SUP>2</SUP>개의 동일한 기본 셀들로 설계되었으며, 셀에 메모리를 사용하지 않았으므로 회로가 간단하며 셀당 TA+TX의 지연시간을 갖는다. 본 논문에서 제안한 곱셈기는 규칙성과 셀 배열에 의한 모듈성을 가지므로 m이 큰 회로의 확장이 용이하며 VLSI회로 실현에 적합할 것이다. In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields GF(3<SUP>m</SUP>), and design the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed (m+1)<SUP>2</SUP> same basic cells. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time TA+TX per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

유한체 GF(p<SUP>m</SUP>)상의 고속 병렬 승산기의 설계

성현경(Hyeon-Kyeong Seong) 한국정보기술학회 2016 한국정보기술학회논문지 Vol.14 No.5

In this paper, we propose a new multiplicative algorithm of two polynomials for irreducible polynomial with all 1 of coefficients on finite fields GF(p<SUP>m</SUP>), and design the high-speed parallel multiplier on finite fields GF(p<SUP>m</SUP>) with input-output module structures using the proposed multiplicative algorithm. The presented high-speed parallel multiplier is designed the basic cells. Since the basic cells could not use a register circuit, the multiplier is very simple. The presented parallel multiplier is used m<SUP>2</SUP> addition gates and m<SUP>2</SUP> multiplication gates, and is short delay time T<SUB>A</SUB> + T<SUB>x</SUB> per cell unit. Total clock time is m unit time. Since the presented high-speed multiplier on finite fields GF(p<SUP>m</SUP>) have regularity and modularity by cell array, it is easy to extend the circuit with large m.

전류모드 CMOS에 의한 4치 가산기 및 승산기의 구현

성현경(Hyeon-Kyeong Seong) 한국정보기술학회 2014 한국정보기술학회논문지 Vol.12 No.1

In this paper, the quarternary adder and multiplier are implemented by current-mode CMOS. First, we implement the quarternary T-Gate using current-mode CMOS which has an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable quarternary addition table and multiplication table over finite fields GF(4) using the quarternary T-gates. We show the characteristics of operation for these circuits by HSpice simulation. These circuits are simulated by MOS model Level 47 Hspice under 0.18μm CMOS standard technology. The simulation results show the satisfying current characteristics. The simulation results of quarternary adder circuit and multiplier circuit using current-mode CMOS show the propagation delay time 0.12㎲, operating speed 300MHz, and consumer power 1.08mW The proposed circuits are reduced the number of transistor, and have a regularity of wiring and modularization, and are suitable for VLSI.

전류모드 CMOS에 의한 3치 가산기 및 승산기의 구현

성현경(Hyeon Kyeong Seong) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under 1.5㎛ CMOS standard technology, 15㎂ unit current. and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

T-Gate에 의한 전류모드 CMOS 3치 가산기 및 승산기의 구현

성현경(Hyeon-Kyeong Seong) 한국정보기술학회 2012 한국정보기술학회논문지 Vol.10 No.3

In this paper, the current-mode CMOS ternary adder and multiplier are implemented by T-Gate. First, we implement the ternary T-Gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-Gates. Finally, We show the characteristics of operation for these circuits simulated by HSpice. These circuits are simulated under 0.18㎛ CMOS standard technology, 5㎂ unit current in 0.54㎛/0.18㎛ ratio of NMOS length and width, and 0.54㎛/0.18㎛ ratio of PMOS length and width, and 2.5V VDD voltage, MOS model Level 47 using HSpice. The simulation results show the satisfying current characteristics. The simulation results of current mode ternary adder circuit and multiplier circuit using T-Gate show the propagation delay time 1.2㎲, operating speed 300KHz, and consumer power 1.08㎽ that ternary adder and multiplier operate a stably.

전류모드 CMOS에 의한 다치논리회로의 설계

성현경(Hyeon Kyeong Seong),강성수(Sung Su Kang),김흥수(Heung Soo Kim) 대한전기학회 1988 대한전기학회 학술대회 논문집 Vol.1988 No.7