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ISM 주파수 대역 송신기를 위한 900-㎒ 집적형 CMOS LC-VCO
이낙원(Nakwon Lee),범진욱(Jinwook Burm) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents a CMOS LC-VCO (Voltage Controlled Oscillator) for ISM band transmitters. To reduce phase noise, varactor gain is minimized, and extra frequency range covered with capacitor bank arrays. And, bias current is controlled by DAC for prevent variations of output power and phase noise. This work is designed with 0.25㎛ RF CMOS process. The VCO gain is 159 ㎒/1V, and power consumption is 1.8~3.6 ㎽. The VCO output phase noise is -119~-130 ㏈c/㎐ at 1 ㎒ offset, and output power is -1.2 ㏈m, at least.
좁은 채널밴드를 갖는 고성능 Phase-locked loops를 위한 새로운 구조의 Charge pump
정윤웅(Youn-woong Chung),범진욱(Jinwook Burm) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
A new charge pump was designed for narrow band phase-locked loop (PLL). The charge pump is a critical element in narrow channel band spacing PLL. The charge pump controlled by phase frequency detector output provides currents to the load capacitor in loop filter. The conventional charge pump has problems of current mismatch, charge sharing, clock feed through, the leakage current, and AC leakage. This problem is improved by the proposed charge pump. So, high performance narrow band PLL is designed by proposed charge pump.
Micro Stacked Spiral Inductor를 이용한 6Gbps 1:2 Demultiplexer 설계
최정명(Jungmyung Choi),범진욱(Jinwook Burm) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.5
CMOS 0.18 ㎛ 공정을 이용하여 1.8V supply voltage에서 6Gbps 이상의 처리속도를 가지는 1:2 demultiplexer(DEMUX)를 구현하였다. 높은 동작속도를 위하여 Current mode logic(CML)의 Flipflop을 사용하였으며 추가적인 동작속도 향상을 위하여 On-chip micro stacked spiral inductor(10×10 ㎛²)를 사용하였다. 총 12개의 인덕터를 사용하여 1200㎛²의 면적증가만으로 Inductive peaking의 효과를 나타낼 수 있었다. Chip의 측정은 wafer상태로 진행하였고 Micro stacked spiral inductor가 있는 1:2 demultiplexer와 그것이 없는 1:2 demultiplexer를 비교하여 측정하였다. 6Gbps에서 측정결과 Micro stacked spiral inductor를 1:2 demultiplexer가 inductor를 사용하지 않은 구조보다 Eye width가 약 3%정도 증가하였고 또한 Jitter가 43% 정도 감소하여 개선효과가 있음을 확인하였다. 소비전력은 76.8㎽, 6Gbps에서의 Eye height는 180㎷로 측정되었다. A 6Gbps 1:2 demultiplexer(DEMUX) IC using 0.18㎛ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of 100㎛² area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8㎽ and eye height was 180㎷ at 6 Gbps.
Offset Cancellation 기법을 적용한 Instrumentation Amplifier 설계
이준규(Jun-Gyu Lee),범진욱(JinWook Burm),임신일(Shin-Il Lim) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
In this paper, we describe the design techniques of instrumentation amplifier for biomedical application using both auto zeroing(AZ) and nested chopping (NC) techniques. We implemented the big resistance with the diode connected PMOS transistors for small die area in the LPF of Nested-chopped IA. The die area of implemented chip were 550㎛ × 200㎛(AZ) and 530㎛ × 300㎛(NC) each. And also shows the offset voltage of 50㎶(AZ) and l100㎵(NC) each at 80㎷ offset with the 0.35㎛ general CMOS technology.
DMB 용 Low Pass Filter 주파수 대역 조절을 위한, 소자의 자동 튜닝 회로
김동영(Dong-young Kim),범진욱(Jinwook Burm) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
The main focus of this paper is CMOS Low-Pass filter with automatic tuning circuit for Digital Media Broadcasting(DMB). This paper provides filter with auto tuning frequency flexibly from process error. Tuning circuit is required because filter coefficients are determined by the product of two dissimilar elements, such as capacitance and resistor values. The proposed Low-Pass filter(LPF) is dissipating 9㎽ from a single UN supply. The 3 ㏈ frequency of LPF is 1.7 ㎒. In addition, it is possible to change 3 ㏈ frequency when reference voltage of tuning circuit in low pass filter is changed. The LPF was fabricated on a 0.18㎛ CMOS technology.
DC Offset Cancellation 회로를 활용한 Programmable Gain Amplifier 설계
김경훈(Kyunghoon Kim),범진욱(Jinwook Burm) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
The main focus of this paper is CMOS programmable gain amplifier (PGA) with DC offset cancellation circuit designs for RF front-end Mobile TV tuners. The proposed PGA is to be operated in 145~1492 ㎒ L-Band for direct conversion system and made for purpose of reducing of layout area. The proposed PGA circuit introduced in this paper has a dynamic range of 40 ㏈ with 2.5 ㏈ gain steps and can operate up to 2 ㎒ dissipating 13.36 ㎽ from a single 3.3V supply. The structures have been fabricated in TSMC 0.18㎛ Technology.