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RISS 인기검색어
- 검색키워드
- 저자 : Namgyu Rye (검색결과 1 건)
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Hyun-Woo Lee,Hoon Choi,Beom-Ju Shin,Kyung-Hoon Kim,Kyung-Whan Kim,Jaeil Kim,Kwang-Hyun Kim,Jong-Ho Jung,Jae-Hwan Kim,Eun-Young Park,Jong-Sam Kim,Jong-Hwan Kim,Jin-Hee Cho,Namgyu Rye,Jun-Hyun Chun,Yuns IEEE 2012 IEEE journal of solid-state circuits Vol.47 No.6
<P>The digital delay-locked loop (DLL) with racing mode and the countered column address strobe (CAS) latency controller are proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power consumption, low jitter, fast locking, wide range of locking, and stuck-free control. The merged dual coarse delay line (MDCDL) reduces the dynamic power consumption of a variable delay line by 30% by sharing a part of the delay line path in DLL. In addition, jitter is reduced by 45 ps in the 1066-DDR3 operating mode by MDCDL. The proposed DLL utilizes an or-and functioned duty cycle corrector (or-and DCC), which consumes 15% of DLL's power, 0.915 pJ/Hz at tCK=1.5 ns and VDD=1.575 V. The countered CAS latency controller (CCLC) saves IDD3N current because it does not need a DLL clock and does not need to be activated for IDD3N (active non-power down) state. The DLL clock is enabled and CCLC is activated only when the read command is issued. This operation condition saves the IDD3N current by 60% with the proposed DLL. The proposed DLL is employed in 128 M×8 DDR3 SDRAM and 64 M×16 DDR3 SDRAM. The former and the latter are fabricated by 5×nm and by 4× nm DRAM process technology, respectively. Experimental results show that ±10% duty error of the external clock can be corrected to within ±2% duty error in less than 512 cycles of locking time under 1.5 ns of tCK. The proposed DLL and CCLC can operate above 1.0-GHz operating frequency at 1.2 V in 5× nm DDR3 SDRAM and at 1.0 V in 4× nm DDR3 SDRAM, respectively. The proposed DLL fabricated with 4× nm technology consumes 6.1 pJ/Hz at 1.575 V.</P>
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