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Seonghearn Lee(이성현) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.9
Sub-0.1㎛로 스케일이 감소함에 따라 기생 저항 효과가 크게 발생되는 dc Ids 측정 데이터 없이 측정 S-파라미터로부터 얻어진 RF Ids를 사용하여 벌크 MOSFET의 포화영역에서 게이트 전압 종속 유효 캐리어 속도를 추출하는 새로운 방법이 개발 되었다. 이 방법은 바이어스 종속 기생 게이트-소스 캐패시턴스와 유효 채널 길이의 복잡한 추출 없이 포화영역의 유효 캐리어 속도를 추출할 수 있게 한다. 이러한 RF 기술을 사용하여 벌크 포화 속도를 초과하는 전자 속도 overshoot 현상이 0.065㎛ 게이트 길이의 벌크 N-MOSFET에서 관찰되었다. A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-0.1㎛. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of 0.065㎛.
Accurate Non-Quasi-Static Gate-Source Impedance Model of RF MOSFETs
Lee, Hyun-Jun,Lee, Seonghearn The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.6
An improved non-quasi-static gate-source impedance model including a parallel RC block for short-channel MOSFETs is developed to simulate RF MOSFET input characteristics accurately in the wide range of high frequency. The non-quasi-static model parameters are accurately determined using the physical input equivalent circuit. This improved model results in much better agreements between the measured and modelled input impedance than a simple one with a non-quasi-static resistance up to 40GHz, verifying its accuracy.
Lee, Sangjun,Lee, Seonghearn The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.6
A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gate-source voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.
Lee, Changjo,Lee, Seonghearn John Wiley Sons, Inc. 2019 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.61 No.4
<P><B>Abstract</B></P><P>A high resistivity PD‐SOI MOSFET equivalent circuit model including a parallel connection of intrinsic output capacitance and conductance with frequency‐dependent empirical equations is newly proposed to accurately simulate their abrupt change in the low‐frequency region. This new empirical model is superior to a conventional RC one, because equivalent circuit structure and parameter extraction process are simpler. Better agreements with measured <I>Y</I><SUB>22</SUB>‐parameter are obtained for the new model than the conventional one.</P>
New SPICE Modeling for Bias-Dependent Gate-Drain Overlap Capacitance in RF MOSFETs
Sangjun Lee(이상준),Seonghearn Lee(이성현) 대한전자공학회 2015 전자공학회논문지 Vol.52 No.4
기존의 BSIM4 모델과 다이오드를 사용한 BSIM4 Macro 모델의 바이어스 종속 게이트-드레인 오버렙 캐패시턴스 Cgdo 시뮬레이션의 부정확성에 대하여 자세히 분석하였다. 이러한 Macro 모델은 기존의 BSIM4 모델보다 더 정확하지만 선형영역에서 사용될 수 없음을 발견하였다. 기존 모델들의 부정확성을 제거하기 위해서 물리적인 바이어스 종속 Cgdo 모델 방정식을 사용한 새로운 BSIM4 Macro 모델을 제안하였고 전체 바이어스 영역에서 유효함을 입증하였다. The inaccuracy of the bias-dependent gate-drain overlap capacitance Cgdo simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. It is found that the accuracy of the macro model is better than of the BSIM4. However, the macro model cannot be used in the linear region. In order to remove the inaccuracy of the conventional models, a new BSIM4 macro model with a physical bias-dependent Cgdo equation is proposed and its accuracy is validated in the full bias range.
Sangjun Lee,Seonghearn Lee 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.6
A new paired gate-source voltage RF capacitance-voltage (C-V) method of extracting the effective channel length and parasitic capacitance using the intersection between two closely spaced linear regression lines of the gate capacitance versus gate length measured from S-parameters is proposed to remove errors from conventional C-V methods. Physically verified results are obtained at the gatesource voltage range where the slope of the gate capacitance versus gate-source voltage is maximized in the inversion region. The accuracy of this method is demonstrated by finding extracted value corresponding to the metallurgical channel length.