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RISS 인기검색어
- 검색키워드
- 저자 : Kimiyoshi Usami (검색결과 5 건)
- 무료
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- 유료
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MTJ Based Non-Volatile Flip Flop to Prevent Useless Store Operation
Masaru Kudo,Kimiyoshi Usami 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
This paper describes a new approach to combine spin transfer torque Magnetic Tunnel Junction (MTJ) based non-volatile flip-flop (NVDFF) is proposed. NVDFF is expected to realize non-volatile power gating which enable anytime power-off and instant power-on. However the conventional NVFF consumes the energy dissipation for storing the data even when the same data is stored to MTJ. In this paper, we propose a new NVDFF to prevent the useless store operation. We design and evaluate the conventional NVDFF and the proposed NVDFF. Simulation results showed that the store energy dissipation reduced to 15-29% at a 16bit counter circuit and ISCAS’89 benchmark circuits.
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Power-Switch Clustering Method for Static Timing Analysis
Tatsunori Hashida,Kimiyoshi Usami 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
A Multiple-Threshold CMOS (MTCMOS) is one of the techniques which reduce leakage power while keeping high performance of LSI. Static Timing Analysis (STA) is an established technique to estimate the delay of circuits. In MTCMOS circuits, the conventional STA cannot be applied. Due to wire resistance of the virtual ground line and channel-resistance of Power-Switch (PS) transistors, the fall delay deviates from that of a CMOS circuit without PS. In addition, the delay is changed by overlapping of discharge currents from each gate. In this paper, we propose a PS clustering technique that makes STA in MTCMOS circuits possible. We create a circuit structure such that the discharge currents from gates do not overlap with each other. Experimental results show that the proposed STA-approach allows us to estimate the delay of the MTCMOS circuit within approximately 12% error.
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Effectiveness of Power Gating for a Superscalar processor
Tetsuya Muto,Kimiyoshi Usami 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
As the miniaturization of manufacturing process gets advanced, leakage power consumption quickly increases and becomes dominant in the total power consumption. Power Gating (PG) is a well-known technique that efficiently reduces leakage power. However effectiveness by applying PG to Functional units of a Superscalar processor has not been studied enough. In this paper, we investigated the effectiveness for a Superscalar processor assuming “2Way” and “4Way” by using a Simplescalar processor simulator with “pisa” architecture. Simulation results for programs in SPEC CPU 2000 and MiBench showed that applying PG to one ALU in four integer ALUs is effective in “4Way.” Effective sleep cycles that gives the net energy-savings occupy 63% in the total execution cycles on average. Applying PG to the integer Mult/Div also contributes to energy reduction. In “2Way,” only applying PG to the integer Mult/Div is effective.
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Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit
Satoshi KOYAMA,Seidai TAKEDA,Kimiyoshi USAMI 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
On cutting-edge semiconductor process, leakage current varies drastically due to process variation and temperature changes. At the circuit design stage, it is difficult to estimate the amount of leakage current at every manufactured chip. Therefore an on-chip function of measuring leakage current is required. The Virtual-ground (VGND) voltage of MTCMOS circuits increases during the sleep operation, because parasitic capacitance of a VGND line is charged up by the leakage current. By applying this behavior, we design leakage monitor circuits using ASPLA 90nm technology. Simulation results show that monitor delay-time is 165ns and monitor-error is 6% under the typical process condition, 25℃ and operating frequency of 200㎒. Power dissipation of designed circuits is 29㎼ in the monitoring mode and 15㎼ in the standby mode.
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Yusuke Umahashi,Yuki Kambayashi,Masaru Kato,Yohei Hasegawa,Hideharu Amano,Kimiyoshi Usami 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
When the dynamic reconfigurable processors run, a lot of Processing Elements (PE) are changed by the context which is written information of circuit configuration. Some PEs execute heavy operations, while other PEs execute light operation. Therefore, the delay time of each PE changes with the contexts. We propose a technique to dynamically change dual supply voltages at each PE. First, we calculate the delay of each PE under the context. Next, we define the standard delay. The standard delay is the longest delay of each PE. Then we assign the standard or lower voltage to each PE. If the PE’s delay at the lower voltage is longer than the standard, this PE is assigned the standard voltage. If shorter than the standard delay, this PE is assigned the lower voltage. Finally, we calculate the power consumption with the technique of dual supply voltage by using the number of assignment the each voltage. When the same voltage was assigned to, the power consumption was reduced by 18.7%. When the voltage is assigned PE-by-PE individually, the power consumption was reduced by 20.3%.
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