Comparative Analysis of SnO_x Thin Films Deposited by RF Reactive Sputtering with Different SnO/Sn Target Compositions

Kim, Cheol,Cho, Seungbum,Kim, Sungdong,Kim, Sarah Eunkyung Electrochemical Society 2017 ECS journal of solid state science and technology Vol.6 No.12

<P>A p-type oxide is a key element for transparent thin-film transistor applications. Among the various p-type oxides currently available, SnO<SUB>x</SUB> deposited by sputtering is the subject of interest in this study for high-performance and reliable thin films. A tin target or a tin oxide target is typically used to fabricate p-type SnO<SUB>x</SUB> during sputtering. A metallic target provides easy control of various film properties and chemical compositions, while a ceramic target offers structural stability and better control of stoichiometry. To use the advantages of both metallic and ceramic targets, a composite target of Sn and SnO was devised, which may provide reliable p-type SnO<SUB>x</SUB> and better control of structural defects. We evaluated four different composition ratios of Sn+SnO targets: a 100 mol% metallic Sn target, a composite target with 50 mol% Sn powder + 50 mol% SnO powder, a composite target with 20% Sn powder + 80 mol% SnO powder, and a 100 mol% ceramic SnO target. SnO<SUB>x</SUB> films were deposited under various sputtering conditions and analyzed structurally, electrically and optically. The composite target with 20 mol% Sn was found to be a promising candidate for p-type SnO<SUB>x</SUB> films, showing >75% transmittance and high mobility up to 9.07 cm<SUP>2</SUP>V<SUP>−1</SUP>s<SUP>−1</SUP>.</P>

Transparent SnO_x thin films fabricated by radio frequency reactive sputtering with a SnO/Sn composite target

Kim, Cheol,Kim, Sungdong,Kim, Sarah Eunkyung Elsevier S.A. 2017 Thin Solid Films Vol.634 No.-

<P><B>Abstract</B></P> <P>SnO<SUB>x</SUB> thin films are potentially excellent conductive material with large hole mobility and have attracted ever-increasing attention for next generation electronic applications. In this study, SnO<SUB>x</SUB> thin films were deposited on a borosilicate glass substrate by radio frequency (rf) reactive sputtering using a SnO/Sn (9:1mol% ratio) composite target. The composite target was used to produce a chemically stable composition of SnO<SUB>x</SUB> thin film while controlling structural defects by chemical reaction between tin and oxygen. The effects of oxygen contents and annealing on various properties of SnO<SUB>x</SUB> thin films were studied. The structural analysis was carried out using X-ray photoelectron spectroscopy and X-ray diffraction. The electrical and optical analyses were performed by the Van der Pauw Hall effect measurement and UV/VIS spectrometer, respectively. SnO<SUB>x</SUB> thin films at P<SUB>O2</SUB> =0% (annealed) and 3% (as deposited) exhibited a p-type conductivity of 0.09–0.11Ω<SUP>−1</SUP> cm<SUP>−1</SUP>, a hole mobility of 0.2–1.2cm<SUP>2</SUP> V<SUP>−1</SUP> s<SUP>−1</SUP>, and a hole concentration of ~10<SUP>18</SUP> cm<SUP>−3</SUP>. Also, these thin films showed the transmittance of about 70% and an optical bandgap of 2.75–3.01eV.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Fabrication of p-type transparent SnO<SUB>x</SUB> thin films by rf sputtering </LI> <LI> SnO:Sn composite target effect on electrical properties of p-type SnO<SUB>x</SUB> thin films </LI> <LI> Study of electrical conductivity conversion of p-type SnO<SUB>x</SUB> thin films </LI> <LI> Annealing effect on electrical properties of p-type SnO<SUB>x</SUB> thin films </LI> </UL> </P>

Challenges of 3D IC Manufacturing

Sarah Eunkyung Kim(김사라은경) 한국정밀공학회 2013 한국정밀공학회 학술발표대회 논문집 Vol.2013 No.10월

Comparative Study of Nitrogen Incorporated SnO₂ Deposited by Sputtering of Sn and SnO₂ Targets

Kim, Youngrae,Kim, Sarah Eunkyung The Korean Ceramic Society 2012 한국세라믹학회지 Vol.49 No.5

Nitrogen-incorporated $SnO_2$ thin films were deposited by rf magnetron sputtering. Comparative structural, electrical and optical studies of thin films deposited by sputtering of the Sn metallic target and sputtering of the $SnO_2$ ceramic target were conducted. The $SnO_2$ thin films deposited by sputtering of the Sn metallic target had a higher electrical conductivity due to a higher carrier concentration than those by sputtering of the $SnO_2$ ceramic target. Structurally the $SnO_2$ thin films deposited by sputtering of the $SnO_2$ ceramic target had a better crystallinity and a larger grain size. This study confirmed that there were distinct and clear differences in electrical, structural, and optical characteristics between $SnO_2$ thin films deposited by reactive sputtering of the Sn metallic target and by direct sputtering of the $SnO_2$ ceramic target.

Effects of forming gas plasma treatment on low-temperature Cu-Cu direct bonding

Kim, Sungdong,Nam, Youngju,Kim, Sarah Eunkyung IOP Publishing 2016 Japanese journal of applied physics Vol.55 No.6

<P>Low-temperature Cu-Cu direct bonding becomes of great importance as Cu is widely used as an interconnection material in the packaging industry. Preparing a clean surface is a key to successful Cu-Cu direct bonding. We investigated the effects of forming gas plasma treatment on the reduction of Cu oxide and Cu-Cu bonding temperature. As plasma input power and treatment time increased, Cu oxide could be effectively reduced, and this could be attributed to the enhanced chemical reaction between forming gas plasma and Cu oxide. When the bonding temperature was reduced from 415 to 300 degrees C, the bonding strength of the plasma-treated interface was increased from 1.8 to 5.55 J/m(2) while that of the wet-treated interface was decreased. (C) 2016 The Japan Society of Applied Physics</P>

IoT 적용을 위한 다종 소자 전자패키징 기술

김사라은경,Kim, Sarah Eunkyung 한국마이크로전자및패키징학회 2016 마이크로전자 및 패키징학회지 Vol.23 No.3

IoT 적용을 위해서는 다종 소자를 높은 connectivity 밀도로 집적화시키는 전자패키징 기술이 매우 중요하다. FOWLP 기술은 입출력 밀도가 높고, 소자의 집적화가 우수하고, 디자인 유연성이 우수하여, 최근 개발이 집중되고 있는 기술이다. 웨이퍼나 패널 기반의 FOWLP 기술은 초미세 피치 RDL 공정 기술과 몰딩 기술 개발이 최적화 되어야 할 것이다. 3D stacking 기술 특히 웨이퍼 본딩 후 TSV를 제조하는 방법(via after bonding)은 가격을 낮추면서 connectivity를 높이는데 매우 효과적이라 하겠다. 하지만 저온 웨이퍼 본딩이나 TSV etch stop 공정과 같이 아직 해결해야할 단위 공정들이 있다. Substrate 기술은 두께를 줄이고 가격을 낮추는 공정 개발이 계속 주목되겠지만, 칩과 PCB와의 통합설계(co-design)가 더욱 중요하게 될 것이다. The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

Wafer-to-Wafer Integration을 위한 생산수율 챌린지에 대한 연구

김사라은경,Kim, Sarah Eunkyung 한국마이크로전자및패키징학회 2013 마이크로전자 및 패키징학회지 Vol.20 No.1

3D integration 기술 특히 W2W integration 기술은 전자산업의 디바이스 scaling 문제를 해결하고 고성능화 소형화 추세에 맞춘 가장 핵심적인 기술 방향이다. 그러나 W2W integration 기술은 현재 가격과 생산수율의 장애를 가지고 있고, 이를 해결하기 위해서 웨이퍼 매칭, 리던던시, 다이 면적 축소, 배선 층 수 축소와 같은 디자인 연구들이 진행되고 있다. W2W integration 기술이 대량생산으로 연결되기 위해서는 우선적으로 웨이퍼 본딩, 실리콘연삭, TSV 배선 공정의 최적화가 이루어져야 하겠지만, 가격을 포함한 생산수율을 높이기 위해서는 반드시 디자인 연구가 선행되어야 하겠다. Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

Fine-pitch 소자 적용을 위한 bumpless 배선 시스템

김사라은경,Kim, Sarah Eunkyung 한국마이크로전자및패키징학회 2014 마이크로전자 및 패키징학회지 Vol.21 No.3

차세대 전자소자는 입출력(I/O) 핀 수의 증가, 전력소모의 감소, 소형화 등으로 인해 fine-pitch 배선 시스템이 요구되고 있다. Fine-pitch 특히 10 um 이하의 fine-pitch에서는 기존의 무연솔더나 Cu pillar/solder cap 구조를 사용할 수 없기 때문에 Cu-to-Cu bumpless 배선 시스템은 2D/3D 소자 구조에서 매우 필요한 기술이라 하겠다. Bumpless 배선 기술로는 BBUL 기술, 접착제를 이용한 WOW의 본딩 기술, SAB 기술, SAM 기술, 그리고 Cu-to-Cu 열압착 본딩 기술 등이 연구되고 있다. Fine-pitch Cu-to-Cu interconnect 기술은 연결 방법에 상관없이 Cu 층의 불순물을 제거하는 표면 처리 공정, 표면 활성화, 표면 평탄도 및 거칠기가 매우 중요한 요소라 하겠다. The demand for fine-pitch devices is increasing due to an increase in I/O pin count, a reduction in power consumption, and a miniaturization of chip and package. In addition non-scalability of Cu pillar/Sn cap or Pb-free solder structure for fine-pitch interconnection leads to the development of bumpless interconnection system. Few bumpless interconnect systems such as BBUL technology, SAB technology, SAM technology, Cu-toCu thermocompression technology, and WOW's bumpless technology using an adhesive have been reviewed in this paper: The key requirements for Cu bumpless technology are the planarization, contamination-free surface, and surface activation.

Experimental assessment of on-chip liquid cooling through microchannels with de-ionized water and diluted ethylene glycol

Won, Yonghyun,Kim, Sungdong,Kim, Sarah Eunkyung IOP Publishing 2016 Japanese journal of applied physics Vol.55 No.6

<P>Recent progress in Si IC devices, which results in an increase in power density and decrease in device size, poses various thermal challenges owing to high heat dissipation. Therefore, conventional cooling techniques become ineffective and produce a thermal bottleneck. In this study, an on-chip liquid cooling module with microchannels and through Si via (TSV) was fabricated, and cooling characteristics were evaluated by IR measurements. Both the microchannels and TSVs were fabricated in a Si wafer by deep reactive ion etching (DRIE) and the wafer was bonded with a glass wafer by a anodic bonding. The fabricated liquid cooling sample was evaluated using two different coolants (de-ionized water and 70 wt% diluted ethylene glycol), and the effect of coolants on cooling characteristics was investigated. (C) 2016 The Japan Society of Applied Physics</P>

Assessment of Spin-on-Glass for Fan-Out Wafer Level Packaging with Multilayer Interconnects

Song, Changmin,Kim, Sungdong,Kim, Sarah Eunkyung American Scientific Publishers 2018 Nanoscience and nanotechnology letters Vol.10 No.9