http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Jiashen Li (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
-
Tingting Duan,Shanjun Liu,Dongying Wang,Jiashen Feng,Ningning Song,Yanxin Yu,Yingxia Li 대한토목학회 2020 KSCE Journal of Civil Engineering Vol.24 No.5
Due to intense human activities, urban street dusts and river sediments are usually polluted by heavy metals. This study investigated the seasonal variations (summer and winter) of pollution level, spatial distribution and potential sources of heavy metals in street dusts (SD) and river sediments (RS) of Dongluo River watershed, Ji’nan, China. Results showed cadmium (Cd), chromium (Cr), copper (Cu), lead (Pb) and zinc (Zn) contents were 3.5 (8.6), 3.0 (1.4), 4.9 (2.6), 4.1 (1.1) and 3.9 (4.0)-fold of their geochemical soil background values (BGV) of Shandong Province, China in summer (winter). Mercury (Hg) and arsenic (As) contents were lower than their background values in both summer and winter. The differences of Cd, Cr, Cu, Pb, Zn, Mn and As contents in river sediments between winter and summer were not statistically significant. The correlation coefficients between metal contents and the distance between sampling sites and the east-west boundary of study area were higher in summer than those in winter. Based on principal component analysis (PCA) and multivariate linear regression (MLR), coal combustion and traffic-related sources were the main sources in winter, and agricultural activities and traffic-related sources were the main sources in summer.
-
Digital Post-processing Techniques for Time-interleaved ADCs
Hongmei Chen,Lanyu Wang,Jian Wang,Jiashen Li,Honghui Deng,Xu Meng,Yongsheng Yin 대한전자공학회 2022 IEIE Transactions on Smart Processing & Computing Vol.11 No.6
This paper presents an all-digital post-processing circuit for a high-speed and highprecision time-interleaved ADC (TIADC). By pre-inputting a test signal in the TIADC, channel mismatch errors are estimated and stored, and the stored values are extracted to compensate for errors when the input signal is at a special frequency. The frequency can be detected by a threshold judgement module. This solves the problem of the traditional modulation calibration algorithm, which cannot calibrate the signal at a special frequency. A high-speed low-complexity digital down converter (DDC) circuit with an optional decimation ratio of 1, 2, 4, or 8 times was designed to have different frequency outputs of the TIADC. We applied it to a four-channel 14-bit 360-MHz TIADC system with an input signal fin of 110 MHz. The FPGA verification results show that after calibration and decimation, the spurious-free dynamic range (SFDR) and signal-to-noise distortion ratio (SNDR) improve by about 40 dB and 30 dB, respectively.
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
