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RISS 인기검색어
- 검색키워드
- 저자 : Borghate Vijay B. (검색결과 6 건)
- 무료
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B. Hemanth Kumar,Makarand M. Lokhande,Raghavendra Reddy Karasani,Vijay B. Borghate 전력전자학회 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.1
In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.
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Kumar, B. Hemanth,Lokhande, Makarand M.,Karasani, Raghavendra Reddy,Borghate, Vijay B. The Korean Institute of Power Electronics 2018 JOURNAL OF POWER ELECTRONICS Vol.18 No.1
In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.
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Suryawanshi Hiralal M.,Borghate Vijay B.,Ramteke Manojkumar R.,Thakre Krishna L. The Korean Institute of Power Electronics 2006 JOURNAL OF POWER ELECTRONICS Vol.6 No.4
This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for ($2{\times}36$ Watt) fluorescent lamps operating at 50 kHz switching frequency and input line voltage (230 V, 50 Hz).
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A Modified Switched-Diode Topology for Cascaded Multilevel Inverters
Raghavendra Reddy Karasani,Vijay B. Borghate,Prafullachandra M. Meshram,H. M. Suryawanshi 전력전자학회 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.5
In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.
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A Modified Switched-Diode Topology for Cascaded Multilevel Inverters
Karasani, Raghavendra Reddy,Borghate, Vijay B.,Meshram, Prafullachandra M.,Suryawanshi, H.M. The Korean Institute of Power Electronics 2016 JOURNAL OF POWER ELECTRONICS Vol.16 No.5
In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results.
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Hiralal M. Suryawanshi,Vijay B. Borghate,Manojkumar R. Ramteke,Krishna L. Thakre 전력전자학회 2006 JOURNAL OF POWER ELECTRONICS Vol.6 No.4
This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for (2 × 36 Watt) fluorescent lamps operating at 50 ㎑ switching frequency and input line voltage (230 V, 50 ㎐).
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