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Improved CMOS Dynamic D-type Flip-Flops for High-Speed Dual-Modulus Prescaler
C. Fangkaew,A. Thanachayanont 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
This paper presents new dynamic D-type flipflops (D-FFs) for high-speed dual-modulus prescaler. Using True-Single-Phase-Clock (TSPC) and ratioed logic techniques, the new DFFs are realized with minimum number of transistors, reduced glitch and charge-sharing problems, and thus enabling very high speed operation. To demonstrate the performance of the proposed DFFs, a divide-by-128/129 dual-modulus prescaler has been realized. Simulation results using Spectre with 0.35-㎛ CMOS process parameters show that the prescaler has the maximum operating frequency of 4.4 ㎓ while dissipating 25.6 ㎽ under a 3.3 V power supply voltage.