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이희덕,한철희,Lee, Heui-Deok,Han, Chul-Hi 대한전자공학회 1990 전자공학회논문지 Vol. No.
동작 속도와 용량성 부하에 따른 최적소자크기를 결정할 수 있는 bipolar-CMOS 버퍼 모델을 제안한다. 면적 최적화를 위한 해석적 결과를 바이폴라의 고주입 효과 및 MOS의 챠넬 속도제한영역을 가정하여 구했다. BICMOS 버퍼의 면적은 용량성 부하에 거의 비례하는 에미터 길이와 챠넬 폭을 정함으로써 최적화된다는 것을 보이고, 회로 세뮬레이션 결과와 비교하여 확인하였다. A model for bipolar-CMOS buffer design is presented which offers a guideline for determining device sizes based on speed and capacitive load. Closed-form solutions for area optimization are obtained assuming high level injection and channel velocity limitation. The solutions and circuit simulations show that the areas of BICMOS buffers are optimized by scaling the emitter length and the channel width approximately in proportion with capacitive load.
나노 CMOS 소자 적용을 위한 질소 분위기에서 형성된 질화막을 이용한 폴리실리콘 적층 구조
호원준,이희덕,Ho, Won-Joon,Lee, Hi-Deok 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.11
A new fabrication method is proposed to form the stacked polysilicon gate by nitridation in $N_2$ atmosphere using conventional LP-CVD system. Two step stacked layers with an amorphous layer on top of a polycrystalline layer as well as three step stacked layers with polycrystalline films were fabricated using the proposed method. SIMS profile showed that the proposed method would successfully create the nitrogen-rich layers between the stacked polysilicon layers, thus resulting in effective retardation of dopant diffusion. It was observed that the dopants in stacked films were piled-up at the interface. TEM image also showed clear distinction of stacked layers, their plane grain size and grain mismatch at interface layers. Therefore, the number of stacked polysilicon layers with different crystalline structures, interface position and crystal phase can be easily controlled to improve the device performance and reliability without any negative effects in nano-scale CMOSFETs.
Color-Filter 및 Microlens를 포함한 CMOS Image Sensor의 Optical Stack 구조 별 Pixel FPN 특성 및 원인 분류
최운일,이희덕,Choi, Woonil,Lee, Hi-Deok 한국전기전자재료학회 2012 전기전자재료학회논문지 Vol.25 No.11
FPN (fixed-pattern-noise) mainly comes from the device or pattern mismatches in pixel and color filter, pixel photodiode leakage in CMOS image sensor. In this paper, optical stack module related pixel FPN was investigated and the classification of pixel FPN contribution with the individual optical module process was presented. The methodology and procedure would be helpful in reducing the greater pixel FPN and distinguishing the complex FPN sources with respect to various noise factors.
$0.18{\mu}m$ CMOS Technology에 인터커넥트 라인에 의한 지연시간의 게이트 폭에 대한 의존성 분석
장명준,이희덕,Jang, Myung-Jun,Lee, Hi-Deok 대한전자공학회 2000 電子工學會論文誌-SD (Semiconductor and devices) Vol.37 No.11
본 논문에서는 인터커넥트 라인을 구동하는 CMOS소자의 게이트 폭의 변화에 따라 소자 및 인터커넥트라인에 의한 RC 지연시간이 어떤 특성을 보이는지에 대하여 분석하였다. 인터커넥트 라인의 캐패시턴스 성분만이 주로 나타나는 구조에서는 MOSFET의 크기가 커질수록 전체 지연시간이 감소하는 특성을 보였다. 반면에 인터커넥트 라인의 저항 및 캐패시턴스 성분이 대등하게 지연시간에 영향을 미치는 구조에서는 전체회로의 지연시간이 최소가 되는 MOSFET 크기가 존재함을 수식적으로 제안하고 실험치와 비교하여 잘맞음을 증명하였다. In this paper, the dependence of interconnect line-induced delay time on the size of CMOSFET gate width is characterized. In case of capacitance dominant interconnect line, the total delay time decreases as transistor size increases. However, there exists a transistor size for minimum total delay time when both of resistance and capacitance of interconnect line become larger than those of transistor. The optimum transistor size for minimum total delay time is obtained using an analytic equation and the experimental results showed good agreement with the calculation.
BCD Platform과의 집적화에 적합한 고성능 Lateral Super Barrier Rectifier의 연구
김덕수,이희덕,Kim, Duck-Soo,Lee, Hi-Deok 한국전기전자재료학회 2015 전기전자재료학회논문지 Vol.28 No.6
This paper suggests a high performance lateral super barrier rectifier (Lateral SBR) device which has the advantages of both Schottky diode and pn junction, that is, low forward voltage and low leakage current, respectively. Advantage of the proposed lateral SBR is that it can be easily implemented and integrated in current BCD platform. As a result of simulation using TCAD, BVdss = 48 V, $V_F=0.38V$ @ $I_F=35mA$, T_j = $150^{\circ}C$ were obtained with very low leakage current characteristic of 3.25 uA.
저온 화학기상증착법 및 급속가열 공정을 이용한 그래핀의 합성
임성규,문정훈,이희덕,유정호,양준모,왕진석,Lim, Sung-Kyu,Mun, Jeong-Hun,Lee, Hi-Deok,Yoo, Jung-Ho,Yang, Jun-Mo,Wang, Jin-Suk 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.12
As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.