http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
2.5㎓ 0.25㎛ CMOS Dual-Modulus 프리스케일러 설계
오근창(K. C. Oh),강기섭(K. S. Kang),박종태(J. T. Park),유종근(C. G. Yu) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.10
A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a 0.25㎛ CMOS process. In the design a new dynamic Dr-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates UP to 2.5㎓ and consumes 3.1㎃ at 2.5㎓ operation.
UHF 대역 RFID 리더 응용을 위한 주파수합성기 설계
김경환(K. H. Kim),오근창(K. C. Oh),박동삼(D. S. Park),유종근(C. G. Yu) 대한전기학회 2007 대한전기학회 학술대회 논문집 Vol.2007 No.10
This paper presents a 900㎒ fractional-N frequency synthesizer for radio frequency identification (RFID) reader using 0.18㎛ standard CMOS process. The IC meets the EPC Class-1 Generation-2 and ISO-18000 Type-C standards. To minimize VCO pulling, the 900㎒ VCO is generated by a 1.8㎓ VCO followed by a frequency divider. The settling time of the synthesizer is less than 20㎛. The frequency synthesizer achieves the phase noise of -105.6㏈c/㎐ at 200㎑ offset. The frequency synthesizer occupies an area of 1.8 × 0.99㎟, and dissipates 8㎃ from a low supply voltage of 1.8V.