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과학기술위성 3호를 위한 스페이스와이어 링크 인터페이스 구현
류상문(Sang-Moon Ryu) 한국항공우주학회 2010 韓國航空宇宙學會誌 Vol.38 No.9
스페이스와이어는 우주비행체 구성 요소들 간의 고속 정보 전달을 위하여 링크 또는 네트워크 형태로 연결시켜주는 표준으로서 기존의 방식보다 저렴한 비용에 뛰어난 성능을 발휘하도록 고안되었다. 스페이스와이어는 ESA, NASA 그리고 JAXA의 다수의 우주 개발 프로그램에 적용되었고 향후 국내의 인공위성 개발 프로그램에 적용될 것이다. 스페이스와이어 기술을 효과적으로 유연하게 적용하기 위해서는 관련 기술의 확보가 필수적이다. 본 논문은 과학기술위성 3호의 대용량 메모리 유닛에 적용되는 스페이스와이어 링크 인터페이스의 개발 결과에 관해 소개한다. SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper, faster on-board data handling in spacecraft. SpaceWire is being widely used on many space missions by ESA, NASA and JAXA, and is expected to be used in future satellite development programs in Korea. For flexible and efficient application of SpaceWire, it is necessary to secure the related technologies. This paper describes the development, implementation and test of a SpaceWire link interface, which will be incorporated in MMU(Mass Memory Unit) of STSAT-3(Science & Technology Satellite-3).
자가 복구 오류 검출 및 정정 회로 적용을 고려한 최적 스크러빙 방안
류상문(Sang-Moon Ryu1) 제어로봇시스템학회 2011 제어·로봇·시스템학회 논문지 Vol.17 No.11
Radiation particles can introduce temporary errors in memory systems. To protect against these errors, so-called soft errors, error detection and correcting codes are used. In addition, scrubbing is applied which is a fundamental technique to avoid the accumulation of soft errors. This paper introduces an optimal scrubbing scheme, which is suitable for a system with auto error detection and correction logic. An auto error detection and correction logic can correct soft errors without CPU’s writing operation. The proposed scrubbing scheme leads to maximum reliability by considering both allowable scrubbing load and the periodic accesses to memory by the tasks running in the system.
실시간 제어 시스템의 결함 허용성을 위한 적응형 체크포인팅 기법
류상문(Sang-Moon Ryu) 제어로봇시스템학회 2009 제어·로봇·시스템학회 논문지 Vol.15 No.6
The checkpointing scheme is a well-known technique to cope with transient faults in digital systems. This paper proposes an adaptive checkpointing scheme for the reliability improvement of real-time control systems. The proposed adaptive checkpointing scheme is based on the previous work about the reliability problem of an equidistant checkpointing scheme. For the derivation of the adaptive scheme, some conditions are introduced which are to be satisfied for the reliability improvement by exploiting an equidistant checkpointing scheme. Numerical data show the proposed adaptive scheme outperforms the equidistant scheme from a reliability point of view.
동시 결함 검출 기능이 있는 실시간 제어 시스템의 결함 허용성을 위한 적응형 체크포인팅 기법
류상문(Sang-Moon Ryu) 제어로봇시스템학회 2011 제어·로봇·시스템학회 논문지 Vol.17 No.1
The checkpointing scheme is a well-known technique to cope with transient faults in digital systems. This paper proposes an adaptive checkpointing scheme for the reliability improvement of real-time control systems with concurrent fault detection capability. With concurrent fault detection capability the effect of transient faults are assumed to be detected with no latency. The proposed adaptive checkpointing scheme is based on the reliability analysis of an equidistant checkpointing scheme. Numerical data show the proposed adaptive scheme outperforms the equidistant scheme from a reliability point of view.
류상문(Sang-Moon Ryu) 제어로봇시스템학회 2009 제어·로봇·시스템학회 논문지 Vol.15 No.11
This paper deals with the time synchronization problem over Space Wire links. SpaceWire is a standard for high-speed links and networks between spacecraft components, which was invented for better, cheaper, faster on-board data handling in spacecraft. The standard defines Time-Code for time distribution over Space Wire network. When a Time-Code is transmitted, transmission delay and jitter is unavoidable. In this paper, a mechanism to remove Time-Code transmission delay and jitter over SpaceWire links is proposed and implemented with FPGA for validation. The proposed mechanism achieves high resolution clock synchronization over Space Wire links, complies with the standard and can be easily adopted over SpaceWire network.
인터리빙 구조를 갖는 메모리의 스크러빙 기법 적용에 따른 신뢰도 해석
류상문(Sang-Moon Ryu) 제어로봇시스템학회 2014 제어·로봇·시스템학회 논문지 Vol.20 No.4
Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.
LEON3 기반 임베디드 시스템을 위한 디버깅 도구 개발
류상문(Sang-Moon Ryu) 제어로봇시스템학회 2014 제어·로봇·시스템학회 논문지 Vol.20 No.4
LEON3 is a 32-bit synthesizable processor based on the SPARC V8. It can be connected to AMBA 2.0 bus and has a 7-stage pipeline, IEEE-754 FPU and 256[KB] cache. It can be easily implemented using FPGA and used for a SoC design. DSU which comes with LEON3 can be used to control and monitor the operation of LEON3. And DSU makes it easy to set a debugging environment for the development of both hardware and software for an embedded systems based on LEON3. This paper presents the summary of the debugging tool for LEON3 based embedded systems. The debugging tool can initialize the target hardware, find out how the target hardware is configured, load application code to a specified memory space and run that application code. To provide users a debugging environment, it can set breakpoints and control the operation of LEON3 correspondingly. And function call trace is one of key functions of the debugging tool.
영상 품질 개선을 위한 FPGA 기반 고속 히스토그램 평활화 회로 구현
류상문,Ryu, Sang-Moon 한국정보통신학회 2019 한국정보통신학회논문지 Vol.23 No.11
영상 품질 개선을 위해 사용되는 히스토그램 평활화 알고리즘은 하드웨어 회로로 구현되면 소프트웨어로 구현된 경우보다 작업 속도 면에서 성능이 훨씬 뛰어나다. FPGA를 이용한 히스토그램 평활화 회로 구현에 대부분의 최신 FPGA에 포함된 곱셈기 회로와 상당량의 SRAM을 이용하고, 파이프라인을 적용하면 히스토그램 평활화 회로의 전체적인 동작 성능을 높일 수 있다. 본 논문은 이와 같은 방법을 적용하여 8비트 심도를 갖는 흑백 영상에 대해 히스토그램 평활화 작업을 고속으로 수행 가능한 FPGA 구현 방법을 제안한다. 제안된 회로는 FIFO를 이용하여 한 개의 영상에 대한 평활화가 진행되는 동안 다음 영상에 대한 히스토그램 계산을 수행할 수 있다. FIFO를 이용한 일부 작업의 시간적 중첩과 내장된 곱셈기 회로 그리고 파이프라인 적용 효과로 회로의 전체적인 성능은 대략 매 클럭마다 한 개의 화소에 대해 히스토그램 평활화를 수행할 수 있다. 그리고 영상을 분할하여 히스토그램 평활화 작업의 일부를 병렬 처리하면 그 성능을 속도 면에서 거의 두 배로 향상할 수 있다. Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.