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김기쁨(Ki Bbeum Kim),우현모(Hyun Mo Woo),최수근(Soo Keun Choi) 한국조리학회 2011 한국조리학회지 Vol.17 No.5
This study aimed to enhance the quality and sensory acceptability of dak-galbi sauce made from general tomatoes, plum tomatoes and canned tomatoes and find the most preferred quality characteristics and tomato type for the production of dak-galbi sauce, Dak-galbi sauce was blended with different concentrations of tomatoes (0%, 10%, 20%, 30%, 40%), As the amount of a tomato addition increased, the moisture contents, L-values, a-values and B-values significantly (p<0.001) increased while salinity, sugar contents and viscosity decreased, The attribute difference test showed that significant differences in such properties as color intensity, pungent flavor, pungent taste, mouthfeel were observed with more tomatoes added, Based on the results of this study, the optimal tomato content for maximizing the overall quality of dak-galbi sauce was 10~20% of general tomatoes or 20% of plum and canned tomatoes, More various kinds of dak-galbi sauce are expected to be developed through this study.
4가지 운영모드와 128/256-비트 키 길이를 지원하는 ARIA-AES 통합 암호 프로세서
김기쁨,신경욱,Kim, Ki-Bbeum,Shin, Kyung-Wook 한국정보통신학회 2017 한국정보통신학회논문지 Vol.21 No.4
This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device. 블록암호 ARIA와 AES를 단일 회로로 통합하여 구현한 이중표준지원 암호 프로세서에 대해 기술한다. ARIA-AES 통합 암호 프로세서는 128-비트, 256-비트의 두 가지 키 길이를 지원하며, ECB, CBC, OFB, CTR의 4가지 운영모드를 지원하도록 설계되었다. ARIA와 AES의 알고리듬 공통점을 기반으로 치환계층과 확산계층의 하드웨어 자원이 공유되도록 최적화 하였으며, on-the-fly 키 스케줄러가 포함되어 있어 평문/암호문 블록의 연속적인 암호/복호화 처리가 가능하다. ARIA-AES 통합 프로세서를 $0.18{\mu}m$공정의 CMOS 셀 라이브러리로 합성한 결과 54,658 GE로 구현되었으며, 최대 95 MHz의 클록 주파수로 동작할 수 있다. 80 MHz 클록 주파수로 동작할 때, 키 길이 128-b, 256-b의 ARIA 모드에서 처리율은 각각 787 Mbps, 602 Mbps로 예측되었으며, AES 모드에서는 각각 930 Mbps, 682 Mbps로 예측되었다. 설계된 암호 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였다.