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A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Hiroyuki Yamauchi 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.1
Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random VT variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing VT variation (σVT). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 ㎚ process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 ㎚ node if σVT can be suppressed to < 70 ㎷ thanks to EOT scaling for LSTP (Low Standby Power) process.
A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Yamauchi, Hiroyuki The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.1
Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.
A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Hiroyuki Yamauchi 대한전자공학회 2009 Journal of semiconductor technology and science Vol.8 No.1
Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random VT variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing VT variation (σVT). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if σVT can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.
AN ALGORITHM FOR SOLVING THE PROBLEM OF CONVEX PROGRAMMING WITH SEVERAL OBJECTIVE FUNCTIONS
Cocan, Moise,Pop, Bogdana 한국전산응용수학회 1999 Journal of applied mathematics & informatics Vol.6 No.1
This work aims to establish an algorithm for solving the problem of convex programming with several objective-functions with linear constraints. Starting from the idea of Rosen's algorithm for solving the problem of convex programming with linear con-straints and taking into account the solution concept from multi-dimensional programming represented by a program which reaches "the best compromise" we are extending this method in the case of multidimensional programming. The concept of direction of min-imization is introduced and a necessary and sufficient condition is given for a s∈Rn direction to be a direction is min-imal. The two numerical examples presented at the end validate the algorithm.