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Telescopic 증폭기를 이용한 고속 LVDS I/O 인터페이스 설계
유관우,김정범 강원대학교 정보통신연구소 2007 정보통신논문지 Vol.11 No.-
This paper presents the design of input/output (I/O) interface circuits for 2.5Gbps operation in a 3.3V 0.35m CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS (low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit operated up to 2.5Gbps. The circuit exhibits a power consumption of 21.04mW.
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황혜원(Hye-Won Hwang),Elad Alon,전정훈(Jung-Hoon Chun),권기원(Kee-Won Kwon) 대한전자공학회 2012 電子工學會論文誌-SD (Semiconductor and devices) Vol.49 No.1
본 논문에서는 수학적 해석을 통해 위상 내삽기(Phase Interpolator, PI)를 최적화하는 설계 방법과 인덕터 부하를 이용하여 고속 동작에 적합하도록 개선한 저전력 PI 구조를 제안한다. 정해진 대역폭과 이득을 가지는 PI의 전력이 최소가 되는 설계기준을 공정에 따라 정해지는 상수의 수식으로 제시한다. 또한, 제안된 인덕더 부하를 사용하는 PI구조는 같은 대역폭과 이득에서 소모 전력을 반으로 줄일 수 있다. 0.13㎛ 1.2V CMOS 공정에서 4개의 위상을 가지는 VCO 출력 신호를 이용하여 7-bit PI를 설계한 결과, 인덕터 부하를 사용하고 제안된 설계 기준에 따라 소모 전력을 최적화 하여 12GHz에서 721.2㎼ 소모한다. This paper presents the design optimization technique for a phase interpolator(PI) and suggests the inductor-loaded PI structure for low power consumption suitable for high-speed applications. An analytical study leads to the design criterion composed of the process constants for the minimum power consumption and the proposed inductor-loaded PI reduces the power by half with determined bandwidth and gain of PI. Designed 7-bit PI using 0.13㎛ 1.2V CMOS technology consumes 721.2㎼ in 12GHz with inductor and the suggested optimization technique.
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A Novel Memory Hierarchy for Flash Memory Based Storage Systems
Yim, Keno-Soo The Institute of Electronics and Information Engin 2005 Journal of semiconductor technology and science Vol.5 No.4
Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.
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Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS
Kyongsu Lee,Jae-Yoon Sim IEEE 2014 IEEE transactions on very large scale integration Vol.22 No.10
<P>This paper describes the characteristics of a half-rate clock-embedded source-synchronous signaling scheme to identify its constraints and to optimize the transceiver topology in the presence of a band-limited channel. The proposed signaling combines the half-rate clock to the common mode of the differential data with its mixing phase off by 0.5 UI. Two transceivers with resistive-load and inductive-load receivers are implemented in 130-nm CMOS technology to verify their feasibility for use as serial links. The prototype transceivers achieve a wide operating frequency range 2.25-6 and 5.6-8 Gb/s, respectively, satisfying bit error rate of <;10<SUP>-12</SUP> measured at Tx-Rx linked configuration by 5-in-long FR4 trace with 2<SUP>31</SUP>-1 PRBS. The power efficiencies of transceivers at maximum data rates are 6.4 and 4.6 mW/Gb/s, respectively.</P>
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