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전류모드 CMOS 4치 논리회로를 이용한 64×64-비트 변형된 Booth 곱셈기 설계
김정범 한국정보처리학회 2007 정보처리학회논문지. 컴퓨터 및 통신시스템 Vol.14 No.4
This paper proposes a 64×64 Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung 0.35㎛ standard CMOS process at a 3.3V supply voltage and unit current 5㎂. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of 7.5×9.4 mm2, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier. 본 논문에서는 CMOS 다치 논리회로를 이용하여 64×64 비트 Modified Booth 곱셈기를 설계하였다. 설계한 곱셈기는 Radix-4 알고리즘을 이용하여, 전류모드 CMOS 4치 논리회로로 구현하였다. 이 곱셈기는 트랜지스터 수를 기존의 전압모드 2진 논리 곱셈기에 비해 64.4% 감소하였으며, 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 설계하였다. 설계한 회로는 2.5V의 공급전압과 단위전류 5㎂를 사용하여, 0.25㎛ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 2진 논리 곱셈기는 7.5×9.4 mm2 의 점유면적에 9.8ns의 최대 전달지연시간과 45.2mW의 평균 전력소모 특성을 갖는 반면, 설계한 곱셈기는 5.2×7.8 mm2 의 점유면적에 11.9ns의 최대 전달지연시간과 49.7mW의 평균 전력소모 특성으로 점유면적이 42.5% 감소하였다.
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저 전압 스윙 기술을 이용한 저 전력 병렬 곱셈기 설계
김정범 한국정보처리학회 2007 정보처리학회논문지. 컴퓨터 및 통신시스템 Vol.14 No.3
본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16×16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16×16 비트 병렬 곱셈기를 설계하였다. 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(PowerDelay) 감소가 이루어졌다. This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16×16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35㎛ standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.
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Antioxidant and Anti-Apoptotic Effect of Melatonin on the Vestibular Hair Cells of Rat Utricles
김정범,정재윤,안진철,이정구,황희준 대한이비인후과학회 2009 Clinical and Experimental Otorhinolaryngology Vol.2 No.1
Objectives. Aminoglycosides are commonly used antibiotic agents, and they are known to generate free oxygen radicals within the inner ear and to cause vestibulo-cochlear toxicity and permanent damage to the sensory hair cells and neurons. Melatonin, a pineal secretory product, has the properties of being a powerful direct and indirect antioxidant. The aim of the present study was to prove the antioxidant effect of melatonin against gentamicin-induced ototoxicty. Methods. The utricular maculae of Sprague-Dawley rats were prepared from postnatal day 2-4, and these maculae were were divided into 6 groups as follows: 1) control, 2) melatonin only, 3) gentamicin only, and 4), 5), and 6) gentamicin plus melatonin (10, 50, and 100 μM, respectively). To count the number of hair cells, 5 utricles from each group were stained with phalloidin-FITC on the 1st, 4th, and 7th days after drug administration. Reactive oxygen species (ROS) was assessed by using the fluorescent probe hydrofluorescent diacetate acetyl ester. The caspase-3 activity was also examined with using the fluorescent caspase-3 substrate and performing Western blotting. Results. The result of this study showed that gentamicin induced the loss of utricular hair cells, and this loss of hair cells was significantly attenuated by co-administration of melatonin. Melatonin reduced ROS production and caspase-3 activation in the gentamicin treated utricular hair cells. Conclusion. Our findings conclusively reveal that melatonin has protective effects against gentamicin-induced hair cell loss in the utricles of rat by inhibiting both ROS production and caspase-3 activity. Objectives. Aminoglycosides are commonly used antibiotic agents, and they are known to generate free oxygen radicals within the inner ear and to cause vestibulo-cochlear toxicity and permanent damage to the sensory hair cells and neurons. Melatonin, a pineal secretory product, has the properties of being a powerful direct and indirect antioxidant. The aim of the present study was to prove the antioxidant effect of melatonin against gentamicin-induced ototoxicty. Methods. The utricular maculae of Sprague-Dawley rats were prepared from postnatal day 2-4, and these maculae were were divided into 6 groups as follows: 1) control, 2) melatonin only, 3) gentamicin only, and 4), 5), and 6) gentamicin plus melatonin (10, 50, and 100 μM, respectively). To count the number of hair cells, 5 utricles from each group were stained with phalloidin-FITC on the 1st, 4th, and 7th days after drug administration. Reactive oxygen species (ROS) was assessed by using the fluorescent probe hydrofluorescent diacetate acetyl ester. The caspase-3 activity was also examined with using the fluorescent caspase-3 substrate and performing Western blotting. Results. The result of this study showed that gentamicin induced the loss of utricular hair cells, and this loss of hair cells was significantly attenuated by co-administration of melatonin. Melatonin reduced ROS production and caspase-3 activation in the gentamicin treated utricular hair cells. Conclusion. Our findings conclusively reveal that melatonin has protective effects against gentamicin-induced hair cell loss in the utricles of rat by inhibiting both ROS production and caspase-3 activity.
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김정범 한국정보처리학회 2010 정보처리학회논문지. 컴퓨터 및 통신시스템 Vol.17 No.3
This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The 16x16 bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung 0.18 ㎛ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. 본 논문에서는 저 전압 스윙 기술을 적용하여 저 전력 회로를 구현하고, 슬립 트랜지스터 (sleep-transistor)를 이용하여 누설전류를 최소화하는 새로운 저 전력 MOS 전류모드 논리회로 (MOS current-mode logic circuit)를 제안하였다. 제안한 회로는 저 전압 스윙 기술을 적용하여 저 전력 특성을 갖도록 설계하였고 고 문턱전압 PMOS 트랜지스터 (high-threshold voltage PMOS transistor)를 슬립 트랜지스터로 사용하여 누설전류를 최소화하였다. 제안한 회로는 16 x 16 비트 병렬 곱셈기에 적용하여 타당성을 입증하였다. 이 회로는 슬립모드에서 기존 MOS 전류모드 논리회로 구조에 비해 대기전력소모가 1/104로 감소하였으며, 정상 동작모드에서 11.7 %의 전력소모 감소효과가 있었으며 전력소모와 지연시간의 곱에서 15.1 %의 성능향상이 있었다. 이 회로는 삼성 0.18 ㎛ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.
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전류모드 CMOS 4치 논리회로를 이용한 64×64-비트 변형된 Booth 곱셈기 설계
김정범,Kim, Jeong-Beom 한국정보처리학회 2007 정보처리학회논문지 A Vol.14 No.4
본 논문에서는 CMOS 다치 논리회로를 이용하여 $64{\times}64$ 비트 Modified Booth 곱셈기를 설계하였다. 설계한 곱셈기는 Radix-4 알고리즘을 이용하여 전류모드 CMOS 4치 논리회로로 구현하였다. 이 곱셈기는 트랜지스터 수를 기존의 전압모드 2진 논리 곱셈기에 비해 64.4% 감소하였으며, 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 설계하였다. 설계한 회로는 2.5V의 공급전압과 단위전류 $5{\mu}A$를 사용하여, $0.25{\mu}m$ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 2진 논리 곱셈기는 $7.5{\times}9.4mm^2$의 점유면적에 9.8ns의 최대 전달지연시간과 45.2mW의 평균 전력소모 특성을 갖는 반면, 설계한 곱셈기는 $5.2{\times}7.8mm^2$의 점유면적에 11.9ns의 최대 전달지연시간과 49.7mW의 평균 전력소모 특성으로 점유면적이 42.5% 감소하였다. This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.
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김정범 대한생물치료정신의학회 2000 생물치료정신의학 Vol.6 No.2
The four general areas to be evaluated in cases of panic disorder are (1) medical status, (2) phenomenology and history of panic auld agoraphobia, (3) comorbidity and history of other psychiatric disorders, and (4) predisposing and precipitating factors for panic attacks and factors maintaining the panic disorder. The assessment also involves information about how panic-disordered individuals behave on the five major response systems and their interaction: cognitive, behavioral, affective, physiological, and social. In order to tap into these different areas and response systems, clinicians should use a variety of measurement techniques: clinical interviews, self-report scales, self-monitoring, behavioral observation, psychophysiological monitoring. The use of a simple, psychometrically sound instrument such as Panic Disorder Severity Scale(PDSS), which considers all of the essential domains of panic disorder, will provide clinicians with an appropriate measure for diagnosing and monitoring patients. The application of this more comprehensive scale for monitoring patient should alert clinicians to reemergence of associated symptoms of panic disorder and allow for the rapid modification of treatment. All of the investigators who conduct any study of panic disorder should consider the essential, recommended, optional measures agreed in Consensus Development Conference on the treatment of panic disorder in 1992 and implement them in their research. Then the results of study from different laboratories will be easier to compare.
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