High-performance Sum Operation with Charge Saving and Sharing Circuit for MRAM-based In-memory Computing

Jangseok Yu,Geonwoo Lee,Taehui Na 대한전자공학회 2024 Journal of semiconductor technology and science Vol.24 No.2

In the era of big data, Von Neumann architectures, with their separation of processor and memory, face limitations in terms of bandwidth and data movement overhead. MRAM-based in-memory computing (IMC) is a promising approach to address these issues, leveraging MRAM to perform simple logical operations directly within memory. However, implementation of n-bit full adder (FA) using pre-charge sense amplifier requires “n + 1” stages. Although carry lookahead adders can reduce the number of stages, it causes significant area overhead, which makes them unsuitable for IMC applications. Therefore, it is important to explore alternatives that can minimize the number of stages. In this paper, we propose a high-performance multi-bit FA utilizing a charge saving and sharing (CSS) circuit that acquires a carry every 4 bits and performs a sum operation every 4 bits in parallel. The CSS circuit-based FA reduces the number of stages to “n/4 + 5”, while minimizing the associated area overhead.

CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System

Yebin Lee,Soontae Kim Institute of Electrical and Electronics Engineers 2016 IEEE transactions on very large scale integration Vol.24 No.5

<P>DRAM is one of the main sources of energy consumption in computer systems. Thus, reducing the energy consumption of DRAM can prolong the lifetime of battery-operated embedded/mobile systems. To this end, we propose a DRAM energy-aware prefetching scheme to increase row buffer hits and idle periods of DRAM by clustering its accesses. Although prefetching schemes have traditionally been used to improve the system performance, utilizing them for the energy conservation of DRAM has yet to be investigated. For such energy conservation, our scheme accurately predicts and clusters potential future DRAM accesses. Clustered DRAM accesses exploit a popular first-ready first-come first-serve memory request scheduling and a power-down mode of DRAM more effectively; the probability of row buffer hits and idle periods is significantly increased by our clustering scheme. As a result, large amounts of row activation and idle energy consumption, which are major energy consumption factors in modern DRAM, can be saved. Our prefetching-based memory traffic-clustering scheme was shown to reduce the power and energy consumption of DRAM and improve its performance by an average of 0.2%, 28.9%, and 15.7%, respectively, for memory-intensive programs.</P>

모바일 실시간 시스템의 전력 절감을 위한 태스크 오프로딩, CPU 전압조절, 메모리 배치 통합 기술

기수민,변규리,조경운,반효경 한국정보과학회 2022 정보과학회논문지 Vol.49 No.11

In this paper, we study real-time task scheduling that aims to minimize power consumption of CPU, memory, and network devices in mobile systems. By defining extended task model and adopting three low-power techniques (i.e., task offloading, CPU voltage scaling, and low-power memory placement), we co-optimize these three techniques, thereby saving power consumption of real-time systems by 76.8% on average. Our scheduling has the ability of rescheduling real-time task set by reconfiguring offloading, DVFS, and memory placement considering variations of network conditions, thereby minimizing power consumption without missing deadlines of given real-time tasks. 본 논문은 모바일 실시간 시스템에서 CPU, 메모리, 네트워크 장치 등에서 소모되는 전력을 동시에 고려하는 저전력 태스크 스케줄링 기술을 연구한다. 확장된 태스크 모델의 정의 및 태스크 오프로딩, CPU 전압 조절, 저전력 메모리 배치 기술 등을 적용하고 이에 대한 최적 조합을 탐색하여 제안한 기술이 실시간 시스템의 전력 소모를 평균 76.8% 절약할 수 있음을 보인다. 또한, 본 연구는 변화하는 네트워크 상황에 맞게 오프로딩, DVFS, 메모리 배치 등을 최적화하여 실시간 태스크 집합의 스케줄링을 보장하면서 전력 절감을 극대화하는 특성을 가진다.

Multiple Leading Zero Pattern Scheme for Non-volatile Memories

Ju Hee Choi,Jong Wook Kwak 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.2

Non-volatile memories (NVMs) spend a significant energy to write data. To overcome the drawback of NVMs, researchers have proposed schemes to eliminate the unnecessary write operations by read-before-write scheme and they have achieved reducing the number of write operations. However, the importance of energy consumption of read operations is overlooked in their works, even though read access to NVM is also an important factor of the total power dissipation. To reduce the number of read operations of NVM, we propose a multiple leading zero pattern (MLZP) scheme by employing small tables which track and store the bit patterns frequently used. If another level of cache requires the data which the pattern table contains, the data is forwarded to the requestor from the pattern table instead of access to last-level cache (LLC). Since the size of pattern table is much smaller than that of the LLC, the total energy consumption for accesses to LLC is decreased. The simulation results show that 30.4% and 34.1% reduction in the total energy consumption are achieved compared to the previous works with STT-RAM and PCM, respectively.

Improving Energy Efficiency and Lifetime of Phase Change Memory using Delta Value Indicator

Ju Hee Choi,Jong Wook Kwak 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.3

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

Improving Energy Efficiency and Lifetime of Phase Change Memory using Delta Value Indicator

Choi, Ju Hee,Kwak, Jong Wook The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.3

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

임베디드 자바에서 에너지 절감을 위한 가비지 컬랙션 설계

손필창,전상호,정근재,정명조,이철훈,최인범 한국차세대컴퓨팅학회 2006 한국차세대컴퓨팅학회 논문지 Vol.2 No.2

정응린의 생애와 추모의 양상 및 의미 연구-의거 430년 기념 추모시를 중심으로-

문복희 국제어문학회 2022 국제어문 Vol.- No.92

This paper examines Jeong Eung-rin’s life (1531-1592) and memorial poems commemorating the 430th anniversary of his death. His courtesy name was Baekin and his clan was based in Hadong. He was a loyal subject who saved his country by sacrificing himself when it was in crisis. He was born and raised in a family that valued loyalty, filial piety, righteousness, propriety and wisdom. During the Imjin War or Japanese Invasion of Korea in 1592, he became a militia commander who combined literary and martial arts with a manly spirit. When Seoul fell to the Japanese invaders and the country was put in jeopardy, Jeong Eung-rin wrote in blood from his own finger to save Joseon, encouraged resistance to the invaders, voluntrily fought the Japanese, and died in a sublime fashion. His dedication as a general was was made possible by his patriotism and philosophical beliefs. With these beliefs, he was able to fight without fear of dying, and exerted wisdom to lead his subordinates and people. General Jeong Eung-rin died in 1592 while fighting bravely to protect Joseon from Japanese invasion. A writing contest was held to commemorate the 430th anniversary of his death. Excellent works were selected and compiled into a collection of poems. Accordingly, this paper analyzes the contents of this collection of memorial poems and examines their significance in relation to life. More specifically, among the 506 memorial poems contained in this collection, this paper highlightspoems written in Chinese characters that showed the spirit of loyalty and national protection, sheds light on their literary world, and examines their aesthetic value. In particular, through this paper the author seek to categorize memorial poems that symbolize Jeong Eung-rin’s life and grasp the spirit contained in them. As a result, this paper classifies memorial in honor of Jeong Eung-rin into three categories, namely: loyalty to the country as a military official, loyalty and filial piety as a civil official, and the spirit of patriotism as a civil and military official. It then examines their significance in connection with his life.

프로그램 실행 지연시간 단축과 소비전력 감소를 위한 명령어 캐시 이미지 일괄 로딩 기법

서효중(Hyo-Joong Suh),김태현(Taehyoun Kim) 한국정보과학회 2013 정보과학회 컴퓨팅의 실제 논문지 Vol.19 No.4

고성능 저전력 임베디드 프로세서와 멀티태스킹 운영체제는 스마트폰과 같은 고성능 모바일 기기의 대중화를 이끌어 왔다. 한편, 시스템의 성능 향상을 위한 CPU 클럭 속도의 상승, 캐시 크기의 증가는 전력 소모를 높이게 되며 이는 전지를 사용하는 모바일 시스템의 약점이 된다. 높은 계산 처리 능력을 요구하는 하는 성능 위주의 기기와 달리 모바일 기기의 경우 이러한 특성을 고려한 성능 개선이 필요하다. 프로그램이 처음 시작되는 부분에서는 최초 액세스로 인한 많은 캐시 실패가 발생하게 되며, 이로인한 많은 DRAM 접근이 발생한다. 본 논문은 이러한 문제에 주목하여 프로그램의 수행이 시작할 때 수반되는 캐시 실패를 최소화하는 캐시 일괄 로딩 기법을 제안한다. 시뮬레이션 결과에 따르면 제안한 기법을 사용할 경우 프로그램 초기화 부분의 캐시 실패 감소와 버스트 캐시 이미지 전송에 의한 메모리의 소비 전력 감소를 얻을 수 있었다. High-performance embedded processors and multitasking operating systems have been accelerating explosive growth of high-performance mobile device market such as smart phones. On the other hand, high power consumption is becoming a vulnerable point for mobile devices with battery, which induced by accelerating CPU clock speed and cache size. Mobile devices differ from computation-oriented devices in that the program running on the mobile devices typically interact with user. And thus the performance optimization efforts for mobile devices should be made accordingly. The memory references at the beginning of the program generate bursty DRAM accesses due to initial misses of the cache. In this paper, we propose a cache image pre-loading method which can suppress most of the cache misses during the program initialization part. Simulation results show that the proposed method can reduce cold misses of the initialization part as well as DRAM power consumption by using burst transfer of cache image.

메모리 효율적인 심층 스파이킹 신경망

이연진(Yeonjin Lee),최수름(Sureum Choi),서영교(Yeongkyo Seo) 한국정보기술학회 2022 Proceedings of KIIT Conference Vol.2022 No.6