ARIA 블록 암호의 소형화 구조

박진섭,김용대,유영갑 충북대학교 컴퓨터정보통신 연구소 2005 컴퓨터정보통신연구 Vol.13 No.2

본 논문에서는 128 비트 ARIA 암호 알고리듬을 소형화시킨 32 비트 하드웨어 구조를 제안하고 있다. 최근 휴대폰을 이용한 금융결제나, 노트북에서 무선 인터넷을 이용한 VPN 접속과 같이 휴대형 장치에서도 보안 서비스가 이루어지고 있다. 휴대형 장치는 제한된 크기와 전력에서 동작하기 때문에 보안서비스를 추가하기위해서는 저전력, 소형화 설계가 요구된다. 본 논문의 ARIA 하드웨어 구조는 이러한 제한된 환경에 적용 가능한 저전력, 소형 구조이다. 제안된 ARIA는 32 비트 구조이다. 소형화를 위해서 4개의 S-box와 32비트 확산 함수를 구현하였다. 또한 복호화할 때 라운드 키 생성에 필요한 확산 함수의 사용하지 않도록 데이터 패스를 수정하였다. 본 논문의 32비트 ARIA는 초기값 생성을 위해 53 클록 사이클이 필요하다. 암/복호화에는 236 클럭 사이클이 요구된다. 32비트 ARIA는 0.35 ㎛ CMOS 공정으로 13,960.5 EG로 구성되었다. This paper presents a 32bit hardware architecture for the ARIA cryptographic algorithm. Recently security service has extended on portable devices such as cellular phones and VPN with wireless Internet at laptops. The mobile units have a limited power with small size demanding a low-power and compact design. The hardware design in this paper is a low-power and compact version of ARIA for the limited mobile environment. The proposed ARIA is based on 32-bit architecture.

Low power cryptographic circuit design

You, Young-Gap,Kim, Seung-Youl,Kim, Young-Dae,Park, Jin-Sub 충북대학교 컴퓨터정보통신 연구소 2006 컴퓨터정보통신연구 Vol.14 No.3

This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip,s 0,35㎛ CMOS process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher processor would be essential for improving security of battery-less wireless sensor networks or RFID.

BUILT-IN TEST STRUCTURE FOR LARGE STATIC RAM CHIPS

You, Young Gap 대한전자공학회 1989 ICVC : International Conference on VLSI and CAD Vol.1 No.1

A comprehensive testable memory design methodology is proposed to solve the difficult SRAM testing problem. Testing time is reduced to a manageable range by introducing a small test circuitry into the SRAM design. High fault coverage is obtained by test patterns derived from the real memory failures such as pattern sensitivity and weak-bit failure problems. On-chip generation of the derived test sequence is implemented by making each row of storage cells into a circular shift register. Using this method, a typical 1M bit SRAM chip can be made self-testing with about 10% circuit overhead, and can be tested in 100 msec. The testing time for larger chips need not increase significantly if the chips are designed using many smaller storage arrays.

Testing of Memories with Tolerable Defects

Young Gap You 대한전자공학회 1991 International Conference on Electronics, Informati Vol.1 No.1

A Study on the Digital One-Chip Composite Signal Generator for FM Stereo Application

Do Young Joung,Dae Yong Kim,Tae Young Lim,Young Gap You 대한전자공학회 1997 대한전자공학회 학술대회 Vol.1997 No.1

Memristor 소자를 이용한 비 휘발성 SRAM 셀

유영갑 ( Young Gap You ),김교태 ( Kyo Tae Kim ) 충북대학교 산업과학기술연구소 2011 산업과학기술연구 논문집 Vol.25 No.1

Some memristor-based non-volatile SRAM cells are proposed and analyzed in terms of cell stability. The proposed cells accommodate memristor elements to retain data under power outage. Memristor elements are introduced into the load elements of conventional SRAM cells through series connection in aggressive designs. Upgraded design employs the snap shot control signal to alleviate the weak noise immunity problem. Massive simulation using commercial tools verifies the cell operation. Verification results show that the non-volatile SRAM cells yield promising noise immunity and excellent static noise margin. The non-volatile SRAM cells can replace the conventional cells without significant circuit modification.

Application of Monodirectional Janus Patch to Oromucosal Delivery System

You, Jae Bem,Choi, Ah Young,Baek, Jieung,Oh, Myung Seok,Im, Sung Gap,Lee, Kyung Eun,Gwak, Hye Sun Wiley (John WileySons) 2015 Advanced Healthcare Materials Vol.4 No.15

The Effects on the Putting Alignment with Golf Balls and Putters Aiming Lines

You-Jin Kim,Young-Gap Jin,Bon-Yeop Koo,Jung-Un Jang,Ki-Choong Mah 대한시과학회 2020 대한시과학회지 Vol.22 No.4

목적 : 골프공과 퍼터의 조준보조선의 유무, 개수 및 골프 경력이 퍼팅 시 정렬에 미치는 영향을 분석하고자 하였다. 방법 : 최근 1년간 필드에서 자신의 평균 점수를 알고 사시와 약시가 없는 43명(48.3±10.07세 및 –0.07± 0.74 logMAR)을 대상자로 선정하였으며, 퍼팅 거리 1.5 m 및 3 m에서 조준보조선이 0개, 1개 및 3개인 골프공 과 1개 및 3개인 퍼터를 이용하여 퍼팅 시 정렬 오차를 측정하였다. 결과 : 골프공 및 퍼터의 조준보조선의 유무, 개수 및 골프 경력에 따른 퍼팅 시 정렬 오차를 분석한 결과, 골 프공 정렬의 정확성은 조준보조선 및 핸디캡에 따른 영향이 없는 것으로 나타났다. 하지만, 퍼터 정렬의 정확성은 조준보조선이 1개인 퍼터에 비해 3개인 퍼터에서 증가한 것으로 나타났고 통계적으로 유의한 차이가 발견되었다. 예상 퍼팅 성공률과 주관적 만족도는 조준보조선이 1개인 골프공 및 퍼터에 비해 3개인 골프공 및 퍼터에서 모두 증가하였다. 결론 : 골프공 및 퍼터의 정렬은 전체 퍼팅 수행 과정의 일부분이며, 골프공 및 퍼터의 조준보조선은 정렬 오차 를 일부 감소시키는 것으로 나타났다. 하지만 보다 명확한 분석을 위해 운동학적 측면과 시기능을 모두 고려한 후 속 연구가 반드시 필요할 것으로 생각된다. Purpose : The purpose of this study was to analyze the effect on the alignment with presence, number and handicap of the golf balls and putters during the putting. Methods : For 43 adult golfers(48.33±10.07 years old and –0.07±0.74 logMAR) who know their average score on the field for the last 1 year and without strabismus and amblyopia were selected as subjects. The alignment errors were measured at a putting distance of 1.5 m and 3 m during the putting, by using the golf balls with 0, 1, and 3 aiming lines and the putters with 1 and 3 aiming lines. Results : As a result of analyzing the alignment errors during the putting in accordance with presence, number and handicap of the golf balls and putters aiming lines, there no effects found that the alignment accuracy of the golf balls accordance with the aiming lines and handicap. However, there was a significant difference found that the putters accuracy increased with 3 lines putter than 1 line putter. Moreover, the predicted putting success rate and subjective satisfaction increased in the golf balls and the putters with 3 lines compared to 1 aiming line. Conclusion : Alignment of the golf balls and putters is part of the entire putting process. The aiming lines of the golf balls and putters have been shown to reduce the alignment errors. However, for a more definite analysis, a follow-up study considering both the kinematic aspect and visual function is necessary.

A Vapor-Phase Deposited Polymer Film to Improve the Adhesion of Electroless-Deposited Copper Layer onto Various Kinds of Substrates

You, Jae Bem,Kim, Shin Young,Park, Yong Jin,Ko, Young Gwan,Im, Sung Gap American Chemical Society 2014 Langmuir Vol.30 No.3

<P>The adhesion of electrodeposited metal film to polymeric circuit board substrate is one of the key elements to successful miniaturization of electronic devices. However, as the size of the circuit pattern continuously decreases, a novel method is urgently required to increase the adhesion of the metal film on the substrate, especially on the smooth surface, which is critical to decrease the minimum feature size of the metal pattern. In this research, we developed an adhesion promoter layer by depositing metal chelating poly(4-vinylpyridine) (P4VP) film onto various organic and inorganic substrates via initiated chemical vapor deposition process (iCVD) to enhance the adhesion between the electroless deposited copper (Cu) layer and the substrate. The highest peel strength obtained between the electroless deposited Cu layer and P4VP coated substrate was 1.22 kgf/cm. Many advantageous characteristics of the adhesion promoter layer, including extreme thinness, the improved adhesion strength, conformal coverage, scalability of the deposition process, and short process time, will prompt the applicability of this adhesion promoter layer to industrial scale production.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/langd5/2014/langd5.2014.30.issue-3/la404251h/production/images/medium/la-2013-04251h_0006.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/la404251h'>ACS Electronic Supporting Info</A></P>

Design and evaluation of KB1 cryptic processor

Lim, Young-Il,Choi, Eun-Ju,Cho, Kyoung-Rok,You, Young-Gap 충북대학교 컴퓨터정보통신 연구소 2005 컴퓨터정보통신연구 Vol.13 No.3

This paper proposes a low power small size design of the KB1 block cipher algorithm aiming to portable applications such as RFIDs and PDAs. The KB1 algorithm comprises a modified Feistel structure processing 64 bits data with 128 bits keys. The key generation employs an on-th-fly scheme, where key generation and encryption can be processed simultaneously. The design has been synthesized based on Hynix 0.35㎛ CMOS process resulting in less than 5,100 equivalent gates. One single encryption using 100kHz clock consumes 86㎼ which is small enough for using ultra low power applications of a RFID type.