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RISS 인기검색어
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- 저자 : Yanjun Wei (검색결과 5 건)
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Shenghai Zhou,Hongbo Xu,Yanjun Wei,Jing Gao,Yue Feng,Ning Wang,Junfeng Gao 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2019 NANO Vol.14 No.8
Heteroatom-doped ordered mesoporous carbons (OMCs) have currently been considered as promising electrode materials for electrochemical sensors due to the combined advantages of ordered mesoporous materials and heteroatom-doped carbon materials. Herein, a novel nitrogen and sulfur co-doped OMCs (N,S-OMC) has been prepared via a nanocasting strategy with an inexpensive methylene blue as single precursor. The obtained mesoporous carbon has platelet morphology, short mesoporous channel together with a large surface area (549 m2/g) as well as rich N- and S-containing functional groups (6.8 at.% N and 2.3 at.% S). Compared with the graphene (GR) and carbon nanotube (CNT) electrode material, the N,S-OMC exhibited a higher electrochemical activity towards the oxidation of herbicide amitrole, ascribable to N,S-OMC's open mesoporous structures and abundant electroactive defect sites on the carbon skeleton. And, an amitrole electrochemical sensor with N,S-OMC modified electrode as working electrode was fabricated, exhibiting a good selectivity, stability, reproducibility and wide linear range of 3–750 μM. Moreover, the N,S-OMC-based electrochemical sensor was proved feasible in river water sample analyses, showing a satisfied recovery ranging from 97.03% to 105.42%. The results not only demonstrate cheap methylene blue can be used as single precursor for the N,S-OMC preparation, but also confirm the N,S-OMC is promising in amitrole sensor fabrication.
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Fenghu Li,Fan Mei,Shuishui Yin,Yanjun Du,Lili Hu,Wei Hong,Jiehui Li 대한부인종양학회 2024 Journal of Gynecologic Oncology Vol.35 No.1
Objective: To compare the efficacy and safety of neoadjuvant chemotherapy combined withconcurrent chemoradiotherapy (NACT+CCRT) vs. concurrent chemoradiotherapy (CCRT) inlocally advanced cer vical cancer (LACC) patients with large tumor masses. Methods: LACC patients with localized tumor diameter >4 cm, were randomly allocated in anunblinded 1:1 ratio to NACT+CCRT or CCRT groups. Patients in the NACT+CCRT group weregiven paclitaxel combined with cisplatin (TP) NACT ever y 3 weeks for 2 cycles, followed byCCRT, with the chemotherapy regimen the same as for NACT. CCRT group were given CCRTwith the same as for NACT. Results: From March 1, 2019, to June 30, 2021, 146 patients were included in the finalanalysis. Sixty-eight (93.2%) patients in the NACT+CCRT group and 66 (90.4%) patientsin the CCRT group completed the expected treatment course. The complete response (CR)rate in the NACT+CCRT group was significantly higher than in the CCRT group (87.7% vs. 67.6%, χ2=54.540, p=0.000). In the NACT+CCRT group, the 1- and 2-year overall sur vival(OS) rates were significantly higher than those in the CCRT group (96% vs. 89% and 89%vs. 79%, χ2=5.737, p=0.017). Additionally, the rate of recurrences and distant metastaseswas significantly lower in the NACT+CCRT group than in the CCRT group (4.11% vs. 7.35%,χ 2=4.059, p=0.021). Most treatment-related adverse events in both groups were grade 3. Conclusion: Compared to CCRT, NACT+CCRT might improve the treatment completionrate, increase CR rate and 1- and 2-year OS rates, and reduce distant metastases rate for LACCpatients with large tumor masses.
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Yan, Jun,Zhang, Wei Korean Institute of Information Scientists and Eng 2011 Journal of Computing Science and Engineering Vol.5 No.2
Different cores typically share the last-level cache in a multi-core processor. Threads running on different cores may interfere with each other. Therefore, the multi-core worst-case execution time (WCET) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interference. This is not supported by current WCET analysis techniques that manly focus on single thread analysis. This paper presents a novel approach to analyze the worst-case cache interference and bounding the WCET for threads running on multi-core processors with shared L2 instruction caches. We propose to use an interference matrix to model inter-thread interference, on which basis we can calculate the worst-case inter-thread cache interference. Our experiments indicate that the proposed approach can give a worst-case bound less than 1%, as in benchmark fib-call, and an average 16.4% overestimate for threads running on a dual-core processor with shared-L2 cache. Our approach dramatically improves the accuracy of WCET overestimatation by on average 20.0% compared to work.
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Computing and Reducing Transient Error Propagation in Registers
Yan, Jun,Zhang, Wei Korean Institute of Information Scientists and Eng 2011 Journal of Computing Science and Engineering Vol.5 No.2
Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.
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Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches
Yan, Jun,Zhang, Wei Korean Institute of Information Scientists and Eng 2011 Journal of Computing Science and Engineering Vol.5 No.1
As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.
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