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Truong Thi Kim Nga,Dong-Soo Lee,Kang-Yoon Lee 대한전자공학회 2016 IEIE Transactions on Smart Processing & Computing Vol.5 No.3
A low insertion–loss, high-isolation switch based on single pole double throw (SPDT) for a 2.4㎓ Bluetooth low-energy transceiver is presented in this paper. In order to increase isolation, the body floating technique is implemented. Based on characteristics whereby the ratio of the sizes of the shunt and the series transistors significantly affect the performance of the switches, the device sizes are optimized. A simple matching network is also designed to enhance the insertion loss. Thus, the SPDT switch has high isolation and low insertion loss without increasing the complexity of the circuit. The proposed SPDT is designed and simulated in a complementary metal-oxide semiconductor 65㎚ process. The switch has a 530㎛ x 270㎛ area and achieves 0.9㏈, 1.78㏈ insertion loss and 40㏈, 41㏈ isolation of transmission, reception modes, respectively.
Nga, Truong Thi Kim,Park, Hyung-Gu,Lee, Kang-Yoon The Institute of Electronics and Information Engin 2014 IEIE Transactions on Smart Processing & Computing Vol.3 No.6
This paper presents a new rectifier with a bootstrapping technique to reduce the effective drop voltage. An all-digital delay locked loop (ADDLL) circuit was also applied to prevent the reverse leakage current. The proposed rectifier uses NMOS diode connected instead of PMOS to reduce the design size and improve the frequency respond. All the sub-circuits of ADDLL were designed with low power consumption to reduce the total power of the rectifier. The rectifier was implemented in CMOS $0.35{\mu}m$ technology. The peak power conversion efficiency was 76 % at an input frequency of 6.78MHz and a power level of 5W.
Kim, Sang-Yun,Park, Young-Jun,Ali, Imran,Nga, Truong Thi Kim,Ryu, Ho-Cheol,Khan, Zaffar Hayat Nawaz,Park, Seong-Mun,Pu, Young Gun,Lee, Minjae,Hwang, Keum Cheol,Yang, Youngoo,Lee, Kang-Yoon Institute of Electrical and Electronics Engineers 2018 IEEE transactions on power electronics Vol.33 No.2
<P>In this paper, a high efficiency dc–dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) and ultralow power applications. The hybrid DPWM core with high linearity and low power consumption is proposed to implement the high efficiency DPWM dc–dc converter. It is composed of a two-step delay control using the counter and delay line. An adaptive window analog to digital converter is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the dc–dc converter. Also, all digital type-III compensator is implemented for the low power and small die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5–3 V to generate the output voltage of 1.2 V. The total active area is 500 μm × 300 μm. The measured peak efficiency of the DPWM dc–dc buck converter is 91.5% with a quiescent current consuming only 130 μA.</P>
A Sub-threshold based 747 nW Resistor-less Low-dropout Regulator for IoT Application
Fatemeh Abbassi,Sung Jin Kim,Abdolhamid Noori,Ji-Hyeon Cheon,Truong Van Cong Thuong,Truong Thi Kim Nga,Kang-Yoon Lee 대한전자공학회 2019 Journal of semiconductor technology and science Vol.19 No.3
This paper presents a curvature-compensated Band-Gap reference used as a reference voltage for a Low-Dropout Regulator. The circuit is totally implemented with only MOS transistors functional from 1.8 V to 3.6 V for Internet of Things (IoT) applications. In designed Ultra-Low Power (ULP) BGR, only one stage high slope proportional-to-absolute temperature (PTAT) voltage generator is employed to compensate complementary-to-absolute temperature (CTAT) voltage generated in the current reference. In addition, cascode tail current is utilized to improve Power Supply Rejection Ratio (PSRR). The proposed BGR-LDO uses only the MOSFETs in the subthreshold region to greatly reduce power consumption, in the other words, BJTs and resistors are removed. Therefore, not only consumed power decreases significantly, but also occupied chip area declines. The proposed BGR-LDO circuit fabricated in a 55 nm CMOS process. It consumes 747 nW power for input voltage of 3.3 V. The measurement results illustrate -55 dB power supply rejection ratio, a TC of 16 ppm/°C within a range of the -40°C to 80°C and line regulation of 4.4 mV/V for supply voltage variation from 1.8 V to 3.6 V. Load regulation is 0.8 mV/mA for load current variation form 0 A to 10 mA. The active area is 190 µm × 390 µm.
Design of an efficient RF-DC voltage multiplier for RF Energy Harvesting Applications
Danial Khan,Hamed Abbasizadeh,Zaffar Hayat Nawaz Khan,Truong Thi Kim Nga,Sang Yun Kim,Ho Cheol Ryu,Kang Yoon Lee 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.1
In this paper, a RF-DC voltage multiplier is presented to efficiently convert RF signals to DC voltages. The proposed circuit uses an internal threshold voltage cancellation (IVC) scheme with auxiliary block to reduce the threshold voltage of forward-biased transistors and minimizes the reverse leakage current of the reverse-biased by dynamically controlling the gate-source voltage of the transistors in the main rectification chain. The proposed circuit is designed in 0.18 um CMOS technology. A three-stage voltage multiplier results in a maximum power conversion efficiency (PCE) of 49.1% at input power level of 0 dBm and at frequency of 900 MHz. The proposed circuit produces an output voltage of 4.94 V at 50 KΩ load.